Runtime efficient multi-stage router flow for circuit designs

A system, comprising:

• one or more hardware processors configured to initiate operations including:
• generating a hybrid routing graph by detecting input interconnect blocks in a circuit design and representing groups of the input interconnect blocks as a plurality of coarsened routing nodes, wherein the plurality of coarsened routing nodes are independent of one another;
• performing a global routing of the circuit design using the hybrid routing graph for a target integrated circuit;
• wherein the hybrid routing graph includes routing nodes and the plurality of coarsened routing nodes, each coarsened routing node including a plurality of constituent routing nodes of the hybrid routing graph corresponding to the input interconnect blocks that are treated as a single node during the global routing;
• and
• performing a detailed routing of the circuit design to generate a legal routing solution for the circuit design;
• wherein the detailed routing is performed by routing, in parallel, nets of the circuit design that were globally routed using the plurality of coarsened routing nodes.

One or more computer-readable storage mediums having program instructions embodied therewith, the program instructions executable by computer hardware to cause the computer hardware to initiate executable operations comprising:

• generating a hybrid routing graph by detecting input interconnect blocks in a circuit design and representing groups of the input interconnect blocks as a plurality of coarsened routing nodes, wherein the plurality of coarsened routing nodes are independent of one another;
• performing a global routing of the circuit design using the hybrid routing graph for a target integrated circuit;
• wherein the hybrid routing graph includes routing nodes and the plurality of coarsened routing nodes, each coarsened routing node including a plurality of constituent routing nodes of the hybrid routing graph corresponding to the input interconnect blocks that are treated as a single node during the global routing;
• and
• performing a detailed routing of the circuit design to generate a legal routing solution for the circuit design;
• wherein the detailed routing is performed by routing, in parallel, nets of the circuit design that were globally routed using the plurality of coarsened routing nodes.