G06F 2119/12
Timing analysis or timing optimisation
G06F2119/12 (Timing analysis or timing optimisation) appears on 2,127 US grants and 1,834 published applications in this corpus.
Search patents in G06F- Granted patents
- 2,127
- Published applications
- 1,834
- Assignees
- 404
- Inventors
- 3,859
- Latest grant
- 1 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 2 | 0 |
| 1991 | 1 | 0 |
| 1992 | 1 | 0 |
| 1993 | 1 | 0 |
| 1994 | 0 | 0 |
| 1995 | 5 | 0 |
| 1996 | 0 | 0 |
| 1997 | 5 | 0 |
| 1998 | 8 | 0 |
| 1999 | 11 | 0 |
| 2000 | 9 | 0 |
| 2001 | 6 | 1 |
| 2002 | 7 | 9 |
| 2003 | 8 | 14 |
| 2004 | 15 | 15 |
| 2005 | 6 | 19 |
| 2006 | 25 | 27 |
| 2007 | 29 | 39 |
| 2008 | 34 | 62 |
| 2009 | 36 | 67 |
| 2010 | 62 | 57 |
| 2011 | 81 | 48 |
| 2012 | 97 | 93 |
| 2013 | 139 | 79 |
| 2014 | 150 | 71 |
| 2015 | 101 | 133 |
| 2016 | 115 | 96 |
| 2017 | 147 | 127 |
| 2018 | 112 | 140 |
| 2019 | 185 | 96 |
| 2020 | 188 | 100 |
| 2021 | 142 | 93 |
| 2022 | 92 | 102 |
| 2023 | 86 | 108 |
| 2024 | 75 | 91 |
| 2025 | 101 | 86 |
| 2026 | 44 | 61 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Automatic waiver generation for filtering violations reported by static analysis1 Sep 2026US 12,724,950 B1Synopsys, Inc.
- Delay calculation with pattern matching for static timing analysis25 Aug 2026US 12,717,991 B2Synopsys, Inc.
- Pre-placement clocking identification and resolution for circuit designs18 Aug 2026US 12,711,298 B2Xilinx, Inc.
- Method and system for use with an electronic design automation (EDA) tool to optimize clock scheduling18 Aug 2026US 12,711,300 B2Texas Instruments Incorporated
- Retiming sequential elements having initital states11 Aug 2026US 12,705,410 B2Xilinx, Inc.
- Method and system for exploring complex mega cells in integrated circuit8 Oct 2026US 2026/0310866 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Optimized inter-integrated circuit communication output driver8 Oct 2026US 2026/0310871 A1STMicroelectronics International N. V.
- Net name swap in netlist of circuit system1 Oct 2026US 2026/0300590 A1International Business Machines Corporation
- System and/or method for selecting circuit features for integrated circuit die1 Oct 2026US 2026/0300596 A1Arm Limited
- Edge-weighted graph neural networks for post-placement interconnect capacitance estimation of analog circuits13 Aug 2026US 2026/0236653 A1Drexel University
Most cited
By later US patents
- Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system311US 5,452,239 AQuickturn Design Systems, Inc. · 1995
- Gate-length biasing for digital circuit optimization245US 7,441,211 B1Blaze Dfm, Inc. · 2008
- Frequency driven layout and method for field programmable gate arrays239US 5,659,484 AXilinx, Inc. · 1997
- Apparatus and methods for wire load independent logic synthesis and timing closure with constant replacement delay cell libraries229US 6,523,156 B2Library Technologies, Inc. · 2003
- Method and system for creating, validating, and scaling structural description of electronic device214US 6,216,252 B1LSI Logic Corporation · 2001