Method and system for use with an electronic design automation (EDA) tool to optimize clock scheduling

A system comprising:

• a processor;
• and
• a memory storing instructions which, when executed by the processor, cause the processor to:
• determine a first design for a logic circuit;
• determine a set of clock anchor points (CAPs) on a clock tree for the logic circuit based on the first design;
• determine slack values on inputs and outputs of a plurality of groups of registers in the logic circuit;
• schedule clock skews for the CAPs associated with the plurality of groups of registers by determining slack values for the inputs and outputs of the plurality of groups of registers;
• add CAPS associated with groups of registers having positive slack values to a list of candidates;
• generate a second design for the logic circuit based on the list of candidates;
• and
• utilize the second design as input to a clock tree synthesis module of an electronic design automation (EDA) tool.

A non-transitory computer readable storage medium storing instructions that, when executed by at least one processor, cause the at least one processor to:

• determine a first design for a logic circuit;
• determine a set of clock anchor points (CAPs) on a clock tree for the logic circuit based on the first design;
• determine slack values on inputs and outputs of a plurality of groups of registers in the logic circuit;
• schedule clock skews for the CAPs associated with the plurality of groups of registers by determining slack values for the inputs and outputs of the plurality of groups of registers;
• add CAPS associated with groups of registers having positive slack values to a list of candidates;
• generate a second design for the logic circuit based on the list of candidates;
• and
• utilize the second design as input to a clock tree synthesis module of an electronic design automation (EDA) tool.