Back to results
US 2026/0300596 A1Published application
System and/or method for selecting circuit features for integrated circuit die
AssigneeArm Limited
InventorsChetan Pinto, Kelageri Nagaraj, Duc Anh Tran, Raghavendra Rao Kota, Srinivasan Mohan, Uday Kiran Gangavelli, Neset Berkan Baran
Life of this patent
Estimating the term…
Abstract
Subject matter disclosed herein relates to devices and techniques for determining aspects of a design for an integrated circuit (IC) die. In one embodiment, circuit implementation options for circuit cells in a design of an IC die may be selected based, at least in part, on associated delay characteristics and power metrics.
Claims20
A method comprising:
- partitioning a design of an integrated circuit (IC) die into a plurality of first partitions including a first plurality of first cells, each of the first cells are implementable by a plurality of selectable circuit implementation options, each of the selectable circuit implementation options having a power characteristic and a delay characteristic;
- for at least one first partition of the plurality of first partitions, identifying one or more of the first cells as having a dominant delay effect on timing paths in the at least one first partition;
- for each of the identified one or more of the first cells having a dominant delay effect on timing paths in the at least one first partition, selecting a selectable circuit implementation option having a lowest delay characteristic;
- and
- for remaining unidentified first cells in the at least one first partition, selecting circuit implementation options to achieve a defined timing goal for an implementation of the design of the IC die while minimizing a power metric for the implementation of the design of the IC die.
2 more elements
An article comprising:
- a storage medium comprising computer-readable instructions stored thereon that are executable by one or more processors of a computing device to:
- partition a design of an integrated circuit (IC) die into a plurality of first partitions including a first plurality of first cells, each of the first cells are implementable by a plurality of selectable circuit implementation options, each of the selectable circuit implementation options having a power characteristic and a delay characteristic;
- for at least one first partition of the plurality of first partitions, identify one or more of the first cells as having a dominant delay effect on timing paths in the at least one first partition;
- for each of the identified one or more of the first cells having a dominant delay effect on timing paths in the at least one first partition, select a selectable circuit implementation option having a lowest delay characteristic;
- and
- for remaining unidentified first cells in the at least one first partition, select circuit implementation options to achieve a defined timing goal for an implementation of the design of the IC die while minimizing a power metric for the implementation of the design of the IC die.
3 more elements
An apparatus, the apparatus comprising:
- a memory;
- and
- one or more processors coupled to the memory to:
- partition a design of an integrated circuit (IC) die into a plurality of first partitions including a first plurality of first cells, each of the first cells are implementable by a plurality of selectable circuit implementation options, each of the selectable circuit implementation options having a power characteristic and a delay characteristic;
- for at least one first partition of the plurality of first partitions, identify one or more of the first cells as having a dominant delay effect on timing paths in the at least one first partition;
- for each of the identified one or more of the first cells having a dominant delay effect on timing paths in the at least one first partition, select a selectable circuit implementation option having a lowest delay characteristic;
- and
- for remaining unidentified first cells in the at least one first partition, select circuit implementation options to achieve a defined timing goal for an implementation of the design of the IC die while minimizing a power metric for the implementation of the design of the IC die.
5 more elements
Dependencies are inferred from the claim text.