Pre-placement clocking identification and resolution for circuit designs
AssigneeXilinx, Inc.
InventorsVeeresh Pratap Singh, Padala V Santhosh, Srinivasan Dasasathyan
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Abstract
Preplacement clock resolution for implementing a circuit design includes, prior to placement of the circuit design, determining, using computer hardware, pairs of clocks of the circuit design that clock synchronous inter-clock data paths. Using the computer hardware, a clock group is generated that includes clocks having a common ancestor clock node from the pairs of clocks. A clock delay group property is set, using the computer hardware, for the clocks of the clock group prior to placement. A placed version of the circuit design is generated using the computer hardware. The circuit design is placed using the clock delay group property as set for the clocks of the clock group.
Claims17
A method, comprising:
- prior to placement of a circuit design, determining, using computer hardware, a pair of clock signals specified by the circuit design that clocks a synchronous inter-clock data path, wherein the pair of clock signals have a common ancestor clock node;
- generating, using the computer hardware, a clock group that includes the pair of clock signals;
- setting, using the computer hardware, a clock delay group property for the clock signals of the clock group prior to placement, wherein the clock delay group property forces a placer to use a common location for a clock root for each clock signal of the clock group, and wherein the clock root of each clock signal is disposed between the common ancestor node and endpoints of the inter-clock data path;
- and
- generating a placed version of the circuit design by placing, using the computer hardware, the circuit design using the clock delay group property as set for the clock signals of the clock group thereby locating the clock root for each clock signal of the pair of clock signals at the common location.
A system, comprising:
- one or more hardware processors configured to initiate operations including:
- prior to placement of a circuit design, determining a pair of clock signals specified by the circuit design that clocks a synchronous inter-clock data path, wherein the pair of clock signals have a common ancestor clock node;
- generating a clock group that includes the pair of clock signals;
- setting a clock delay group property for the clock signals of the clock group prior to placement, wherein the clock delay group property forces a placer to use a common location for a clock root for each clock signal of the clock group, and wherein the clock root of each clock signal is disposed between the common ancestor node and endpoints of the inter-clock data path;
- and
- generating a placed version of the circuit design by placing the circuit design using the clock delay group property as set for the clock signals of the clock group thereby locating the clock root for each clock signal of the pair of clock signals at the common location.
A computer program product comprising one or more computer readable storage mediums having program instructions embodied therewith, wherein the program instructions are executable by computer hardware to cause the computer hardware to initiate executable operations comprising:
- prior to placement of a circuit design, determining a pair of clock signals specified by the circuit design that clocks a synchronous inter-clock data path, wherein the pair of clock signals have a common ancestor clock node;
- generating a clock group that includes the pair of clock signals;
- setting a clock delay group property for the clock signals of the clock group prior to placement, wherein the clock delay group property forces a placer to use a common location for a clock root for each clock signal of the clock group, and wherein the clock root of each clock signal is disposed between the common ancestor node and endpoints of the inter-clock data path;
- and
- generating a placed version of the circuit design by placing the circuit design using the clock delay group property as set for the clock signals of the clock group thereby locating the clock root for each clock signal of the pair of clock signals at the common location.
Dependencies are inferred from the claim text.