G06F 2117/10
Buffer insertion
G06F2117/10 (Buffer insertion) appears on 36 US grants and 22 published applications in this corpus.
Search patents in G06F- Granted patents
- 36
- Published applications
- 22
- Assignees
- 15
- Inventors
- 69
- Latest grant
- 8 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2015 | 1 | 1 |
| 2016 | 0 | 0 |
| 2017 | 2 | 1 |
| 2018 | 0 | 0 |
| 2019 | 0 | 0 |
| 2020 | 5 | 0 |
| 2021 | 9 | 4 |
| 2022 | 5 | 1 |
| 2023 | 5 | 5 |
| 2024 | 3 | 3 |
| 2025 | 4 | 5 |
| 2026 | 2 | 2 |
By publication year. 2026 runs to 8 Oct.
Recent patents
- Systems and methods for deploying frame-based simulation models on programmable logic devices8 Sep 2026US 12,730,953 B1The Math Works, Inc.
- Synthesis of a network-on-chip (NoC) for insertion of pipeline stages13 Jan 2026US 12,524,590 B2Arteris, Inc.
- Skewing level limited clock tree23 Sep 2025US 12,423,501 B1Cadence Design Systems, Inc.
- Semiconductor device and method of failure analysis for semiconductor device24 Jun 2025US 12,339,321 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Multi-layer integrated circuit routing tool24 Jun 2025US 12,340,161 B2International Business Machines Corporation
- System and method for insertion of pipeline stages in and synthesis of a network-on-chip (noc)21 May 2026US 2026/0141145 A1Arteris, Inc.
- Heterogeneous integration of components onto compact devices using moiré based metrology and vacuum based pick-and-place1 Jan 2026US 2026/0005060 A1Board of Regents, The University of Texas System
- Heterogeneous integration of components onto compact devices using moiré based metrology and vacuum based pick-and-place18 Dec 2025US 2025/0385120 A1Board of Regents, The University of Texas System
- Heterogeneous integration of components onto compact devices using moiré based metrology and vacuum based pick-and-place18 Dec 2025US 2025/0385121 A1Board of Regents, The University of Texas System
- Local clock buffer with antenna diode feature27 Nov 2025US 2025/0363279 A1International Business Machines Corporation
Most cited
By later US patents
- Automatic pipelining of NoC channels to meet timing and/or performance23US 9,569,579 B1NetSpeed Systems · 2017
- Delay monitoring scheme for critical path timing margin21US 11,409,323 B2Arm Limited · 2022
- Virtual repeater insertion6US 11,144,688 B1Diakopto, Inc. · 2021
- Automatic pipelining of NoC channels to meet timing and/or performance4US 9,158,882 B2NetSpeed Systems · 2015
- Layer assignment technique to improve timing in integrated circuit design3US 10,860,764 B1Cadence Design Systems, Inc. · 2020