Skewing level limited clock tree

A non-transitory computer readable medium comprising instructions, that when executed by a processor, configure the processor to perform operations comprising:

• accessing, from memory, a circuit design comprising a clock tree that interconnects a clock source to a plurality of clock sinks, each clock sink in the plurality of clock sinks having an associated target insertion delay adjustment, the clock tree comprising a restriction on a quantity of levels of components for respectively adding delay to the clock source;
• identifying an individual target insertion delay adjustment associated with an individual clock sink of the plurality of clock sinks;
• comparing the individual target insertion delay adjustment to a threshold value;
• selectively removing the restriction on the quantity of levels of components to provide the individual target insertion delay adjustment based on comparing the individual target insertion delay adjustment to the threshold value;
• and
• modifying at least a portion of the clock tree based on application of the restriction after the selectively removing.

A system comprising:

• one or more processors;
• and
• a memory storing instructions that, when executed by the one or more processors, cause the system to perform operations comprising:
• accessing, from memory, a circuit design comprising a clock tree that interconnects a clock source to a plurality of clock sinks, each clock sink in the plurality of clock sinks having an associated target insertion delay adjustment, the clock tree comprising a restriction on a quantity of levels of components for respectively adding delay to the clock source;
• identifying an individual target insertion delay adjustment associated with an individual clock sink of the plurality of clock sinks;
• comparing the individual target insertion delay adjustment to a threshold value;
• selectively removing the restriction on the quantity of levels of components to provide the individual target insertion delay adjustment based on comparing the individual target insertion delay adjustment to the threshold value;
• and
• modifying at least a portion of the clock tree based on application of the restriction after the selectively removing.