Layer assignment technique to improve timing in integrated circuit design

A method for electronic design automation, the method comprising:

• accessing, from a memory, an initial placement layout of a net of an integrated circuit (IC) design, the IC design comprising multiple layers;
• identifying multiple candidate insertion points in the initial placement layout of the net, the multiple candidate insertion points including candidate insertion points in each layer of the multiple layers;
• generating, using one or more processors of a machine, a plurality of buffer insertion candidates using the multiple candidate buffer insertion points, multiple buffer types, and multiple layer assignments from among multiple layers of the IC design, the generating of the plurality of buffer insertion candidates including generating buffer insertion candidates for each layer assignment by inserting each buffer type of the multiple buffer types at each candidate buffer insertion point;
• determining timing characteristics of each buffer insertion candidate in the plurality of buffer insertion candidates;
• determining a timing improvement provided by each buffer insertion candidate based on respective timing characteristics;
• selecting a buffer insertion candidate from the plurality of buffer insertion candidates based on the timing improvement provided by the buffer insertion candidate;
• and
• assigning the net to a layer in the IC design based on the selected buffer insertion candidate.

A computer-storage medium storing instructions, which when executed by a machine, cause the machine to perform operations comprising:

• accessing, from a memory, an initial placement layout of a net of an integrated circuit (IC) design, the IC design comprising multiple layers;
• identifying multiple candidate insertion points in the initial placement layout of the net, the multiple candidate insertion points including candidate insertion points in each layer of the multiple layers;
• generating, using one or more processors of a machine, a plurality of buffer insertion candidates using multiple candidate buffer insertion points, multiple buffer types, and multiple layer assignments from among multiple layers of the IC design, the generating of the plurality of buffer insertion candidates including generating buffer insertion candidates for each layer assignment by inserting each buffer type of the multiple buffer types at each candidate buffer insertion point;
• determining a net delay associated with a buffer insertion candidate;
• determining a timing improvement of the buffer insertion candidate based on the net delay associated with the buffer insertion candidate;
• selecting the buffer insertion candidate from the plurality of buffer insertion candidates based on the timing improvement provided by the buffer insertion candidate;
• and
• assigning the net to a layer in the design based on the selected buffer insertion candidate.