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US 9,158,882 B2Granted
Automatic pipelining of NoC channels to meet timing and/or performance
AssigneeNetSpeed Systems
InventorSailesh Kumar
Life of this patent
Estimating the term…
Abstract
Systems and methods for automatically generating a Network on Chip (NoC) interconnect architecture with pipeline stages are described. The present disclosure includes example implementations directed to automatically determining the number and placement of pipeline stages for each channel in the NoC. Example implementations may also adjust the buffer at one or more routers based on the pipeline stages and configure throughput for virtual channels.
Claims14
A method, comprising:
- generating a Network on Chip (NoC) comprising a plurality of channels and a plurality of routers, the NoC configured with one or more pipeline stages that are positioned at one or more of the plurality of channels in the NoC based on an associated system on chip (SoC) floorplan and a NoC topology;
- for each of the plurality of channels in the NoC, generating an output register for a corresponding one of the plurality of routers handling output for the each of the one or more channels in the NoC based on a setup time of the corresponding router and a timing path within the corresponding router;
- and
- configuring a physical SoC with the generated NoC and generated output registers.
1 more element
A non-transitory computer readable storage medium storing instructions for executing a process, the instructions comprising:
- generating a Network on Chip (NoC) comprising a plurality of channels and a plurality of routers, the NoC configured with one or more pipeline stages that are positioned at one or more of the plurality of channels in the NoC based on an associated system on chip (SoC) floorplan and a NoC topology;
- for each of the plurality of channels in the NoC, generating an output register for a corresponding one of the plurality of routers handling output for the each of the one or more channels in the NoC based on a setup time of the corresponding router and a timing path within the corresponding router;
- and
- configuring a physical SoC with the generated NoC and generated output registers.
1 more element
Dependencies are inferred from the claim text.