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US 2026/0141145 A1Published application
SYSTEM AND METHOD FOR INSERTION OF PIPELINE STAGES IN AND SYNTHESIS OF A NETWORK-ON-CHIP (NoC)
AssigneeArteris, Inc.
InventorsBenoit De LESCURE, Moez CHERIF
Life of this patent
Estimating the term…
Abstract
A tool makes modifications to the chip floorplan and the network-on-chip (NoC) elements' position on the floorplan and updates the number and position of the pipeline elements in a pipeline stage automatically, resulting in fewer errors and higher productivity.
Claims7
An electronic design tool that implements a method for synthesis and generation of a network-on-chip (NoC), the tool including memory for storing code that is executed by a processor to cause the tool to:
- access a computer-readable description of the NoC, wherein the description of the NoC includes element and connections between each element;
- receive a plurality of performance requirements for the NoC;
- and
- add at least one new pipeline element to produce a pipeline stage along at least one connection within the NoC when data spanning along the at least one connection takes longer than an allowed clock cycle to propagate along the at least one connection;
- update a NoC description with the added new pipeline stage,
- wherein the pipeline stage on the connection is needed to ensure a legal NoC description that satisfies the plurality of performance requirements.
3 more elements
A method comprising:
- taking as input a computer-readable description of a network-on-chip (NoC) having a position of each of a plurality of NoC elements on a floorplan of the NoC;
- calculating, for a connection between two NoC elements selected from the plurality of NoC elements, a number of clock cycles required for data to travel between the NoC elements;
- comparing, for the connection between the two NoC elements, the number of clock cycles required to a number of pipelines already existing on the connection;
- adding a new pipeline element along the connection if a result of the comparison is that there are less pipeline stages on the connection than needed;
- and
- generating an updated NoC description.
3 more elements
A tool, which has a graphical user interface and an input means, for synthesis of a network-on-chip (NoC) topology, the tool comprising:
- a receiving module for taking a computer-readable description of a network-on-chip (NoC), wherein the computer-readable description includes a position of a plurality of NoC elements on a chip floorplan of the NoC;
- a calculation module for calculating a number of clock cycles required for an electric signal to travel between the two NoC elements for a connection between the two NoC elements;
- a comparison module for comparing the number of clock cycles required as calculated to a number of pipelines already existing on the connection between the two NoC elements;
- an adding module for adding a new pipeline element along the connection if a result of the comparison is that there are less pipelines on the connection than needed;
- a removing module for removing an existing pipeline element along with the connection if the result of the comparison is that there are more pipelines on the connection than needed;
- and
- a generator module for generating an updated position for pipeline elements when a new pipeline has been added to the connection or an existing pipeline has been removed from the connection.
4 more elements
Dependencies are inferred from the claim text.