Semiconductor device and method of failure analysis for semiconductor device

A semiconductor device, comprising:

• a first cell (11/14) having an output terminal (111/142), wherein the output terminal has a first potential;
• a snorkel structure (20) comprising:
• a first conductive structure (21) electrically connected to the output terminal of the first cell;
• a first conductive layer (22) electrically connected to the first conductive structure;
• and
• a second conductive structure (23) electrically connected to the first conductive layer (22) and comprising a topmost conductive layer (233), wherein the topmost conductive layer (233) has a second potential substantially the same as the first potential,
• wherein the topmost conductive layer (233) is configured to receive a first e-beam signal.

A method comprising:

• fabricating transistors with a front-end-of-line processing, wherein one of the transistors has a drain terminal connected to an output terminal of a scan flip-flop circuit;
• forming a first conductive structure that is conductively connected to the output terminal, wherein forming the first conductive structure comprises fabricating a plurality of landing portions in multiple metal layers and fabricating a plurality of conductive vias in multiple layers of interlayer dielectric, and wherein each of the conductive vias of the plurality of conductive vias is conductively connected between two of the landing portions;
• and
• fabricating a second conductive structure that is conductively connected to the output terminal of the scan flip-flop circuit through the first conductive structure, and wherein the second conductive structure has a topmost conductive layer configured to receive an e-beam signal.