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US 12,730,953 B1Granted
Systems and methods for deploying frame-based simulation models on programmable logic devices
AssigneeThe Math Works, Inc.
InventorsKiran K. Kintali, Navaneetha K. Ruthramoorthy, Megan N. Carpenter
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Abstract
Systems and methods transform frame-based algorithms into revised algorithms having the same behavior as the frame-based algorithms, but that can be synthesized in hardware. The frame-based algorithm may be represented by an executable simulation model, such as a block diagram model.
Claims11
A computer-implemented method comprising:
- accessing an executable simulation model configured to receive frame-based input data, wherein the executable simulation model includes (i) one or more frame-based signals having a datatype and a rate and (ii) a component configured to perform one or more frame-based operations and produce frame-based output data, the component performing at least one of an elementwise operation, a neighborhood operation, a reduction operation, an iteration operation, a structured access operation, or a random access operation;
- generating, by one or more processors, hardware description language (HDL) code for the executable simulation model, wherein the generating the HDL code includes:
- updating the datatype of the one or more frame-based signals to a new datatype;
- updating the rate of the one or more frame-based signals to a new rate;
- converting the frame-based input data to streaming input data;
- converting the frame-based output data to streaming output data;
- converting the one or more frame-based signals to one or more streaming signals;
- converting the component performing the at least one of the elementwise operation, the neighborhood operation, the reduction operation, the iteration operation, the structured access operation, or the random access operation to a sample-based implementation operating on the one or more streaming signals;
- inserting first logic for generating a ready signal indicating the converted component is ready to process input data;
- inserting second logic for generating a data valid signal indicating output data computed by the converted component is valid;
- adding an input buffer and an output buffer;
- configuring the input buffer to receive the streaming input data and to provide the streaming input data to the converted component in response to the ready signal;
- and
- configuring the output buffer to store the output data in response to the data valid signal and to provide the output data as the streaming output data.
11 more elements
Dependencies are inferred from the claim text.