G06F 13/4009
With data restructuring
Official title: {with data restructuring}
G06F13/4009 (With data restructuring) appears on 751 US grants and 494 published applications in this corpus.
Search patents in G06F- Granted patents
- 751
- Published applications
- 494
- Assignees
- 265
- Inventors
- 1,445
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 0 | 0 |
| 1979 | 1 | 0 |
| 1980 | 2 | 0 |
| 1981 | 0 | 0 |
| 1982 | 2 | 0 |
| 1983 | 2 | 0 |
| 1984 | 4 | 0 |
| 1985 | 3 | 0 |
| 1986 | 5 | 0 |
| 1987 | 3 | 0 |
| 1988 | 7 | 0 |
| 1989 | 5 | 0 |
| 1990 | 2 | 0 |
| 1991 | 7 | 0 |
| 1992 | 10 | 0 |
| 1993 | 5 | 0 |
| 1994 | 16 | 0 |
| 1995 | 17 | 0 |
| 1996 | 22 | 0 |
| 1997 | 28 | 0 |
| 1998 | 39 | 0 |
| 1999 | 39 | 0 |
| 2000 | 34 | 0 |
| 2001 | 12 | 6 |
| 2002 | 17 | 8 |
| 2003 | 10 | 15 |
| 2004 | 17 | 20 |
| 2005 | 13 | 21 |
| 2006 | 16 | 17 |
| 2007 | 14 | 21 |
| 2008 | 24 | 17 |
| 2009 | 15 | 12 |
| 2010 | 21 | 15 |
| 2011 | 18 | 12 |
| 2012 | 15 | 14 |
| 2013 | 13 | 17 |
| 2014 | 19 | 27 |
| 2015 | 22 | 26 |
| 2016 | 23 | 20 |
| 2017 | 18 | 24 |
| 2018 | 34 | 23 |
| 2019 | 32 | 28 |
| 2020 | 19 | 24 |
| 2021 | 24 | 28 |
| 2022 | 24 | 26 |
| 2023 | 20 | 22 |
| 2024 | 22 | 22 |
| 2025 | 23 | 14 |
| 2026 | 12 | 15 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Liquid ejection apparatus, recording medium, and liquid ejection head6 Oct 2026US 12,752,528 B2Konica Minolta, Inc.
- Tunneling of peripheral-bus protocol traffic over coherent fabric and chip-to-chip or die-to-die bus15 Sep 2026US 12,737,314 B2Mellanox Technologies, Ltd.
- Ungrouping and grouping of system busses using link macros capable of joining and splitting2 Jun 2026US 12,645,630 B2Microsoft Technology Licensing, LLC
- System and method for flexibly crossing packets of different protocols12 May 2026US 12,625,836 B2Microchip Technology Incorporated
- Computer architecture having selectable parallel and serial communication channels between processors and memory5 May 2026US 12,619,276 B2Wisconsin Alumni Research Foundation
- Computer Architecture Having Selectable, Parallel and Serial Communication Channels Between Processors and Memory6 Aug 2026US 2026/0227822 A1Wisconsin Alumni Research Foundation
- Asymmetric partial link width state management6 Aug 2026US 2026/0228139 A1
- Low-latency word alignment for serdes interfaces using inline patterns30 Jul 2026US 2026/0219701 A1QUALCOMM Incorporated
- Frequency-dependent data width negotiation for backwards-compatible links like pci-express and compute express link30 Jul 2026US 2026/0220066 A1
- Providing flexible link width (flw) dual 32-bit (x32) links in universal chiplet interconnect express (ucie) 64-bit (x64) modules in processor-based devices23 Jul 2026US 2026/0211831 A1QUALCOMM Incorporated
Most cited
By later US patents
- Bus bridge device including data bus of first width for a first processor, memory controller, arbiter circuit and second processor having a different second data width395US 5,909,559 ATexas Instruments Incorporated · 1999
- Fibre channel to SCSI addressing method and system204US 6,041,381 ACrossroads Systems, Inc. · 2000
- Apparatus, system, and method for bus link width optimization179US 7,136,953 B1NVIDIA Corporation · 2006
- Microprocessor system169US 4,860,198 AKabushiki Kaisha Toshiba · 1989
- Scatter gather memory system for a hardware accelerated command interpreter engine168US 6,105,075 AAdaptec, Inc. · 2000