Microprocessor system

A microprocessor system comprising:

• microprocessor means, coupled to a first 2n-bit data bus and a first control bus, said first 2n-bit data bus including first and second data buses each having an n-bit data width, and responsive to an input 2n-bit data transfer command, for outputting a transfer instruction onto said first control bus, for selectively inputting into said microprocessor means 2n-bit input data on said first 2n-bit data bus, and for selectively outputting from said microprocessor means 2n-bit output data onto said first 2n-bit data bus, an operation state of said microprocessor means being held in accordance with a wait instruction input thereto;
• read/write control means, coupled to said first control bus and a second control bus and responsive to the transfer instruction from said microprocessor means and a disable instruction input thereto, for selectively and sequentially generating and outputting onto said second control bus first and second transfer instructions, the first and second transfer instructions being associated with first and second transfer cycles, respectively;
• bus converter means, coupled to said first 2n-bit data bus and a second 2n-bit data bus including third and fourth data buses and responsive to an input bus conversion instruction, for selectively and sequentially inputting into said bus converter means first n-bit input data ("FNID") and second n-bit input data ("SNID") on said third data bus, for substantially simultaneously outputting from said bus converter means the FNID and SNID as the 2n-bit input data onto said first 2n-bit data bus, for selectively inputting into said bus converter means the 2n-bit output data comprising first n-bit output data ("FNOD") and second n-bit output data ("SNOD") on said first 2n-bit data bus, and for sequentially outputting from said bus converter means the FNOD and the SNOD onto said third data bus;
• a device having the n-bit data width, coupled to said third data bus and said second control bus and responsive to the first and second transfer instructions, for selectively and sequentially outputting from said device the FNID and SNID onto said third data bus, and for selectively and sequentially inputting into said device the FNOD and the SNOD on said third data bus;
• and
• timing generating means, coupled to said second control bus and responsive to the first and second transfer instructions from said read/write control means and an input address, for generating and outputting to said bus converter means the bus conversion instruction, for generating and outputting to said read/write control means the disable instruction between the first and second transfer cycles, and for generating and outputting to said microprocessor means the wait instruction from a first timing during the first transfer cycle to a second timing during the second transfer cycle.