PROVIDING FLEXIBLE LINK WIDTH (FLW) DUAL 32-BIT (x32) LINKS IN UNIVERSAL CHIPLET INTERCONNECT EXPRESS (UCIe) 64-BIT (x64) MODULES IN PROCESSOR-BASED DEVICES

A processor-based device, comprising:

• means for determining, during a first initialization of the processor-based device, that a Universal Chiplet Interconnect Express (UCIe) 64-bit (x64) module of the processor-based device supports Flexible Link Width (FLW);
• means for determining, during the first initialization of the processor-based device, that the UCIe x64 module is communicatively coupled to a first UCIe 32-bit (x32) module and a second UCIe x32 module that require a first x32 link and a second x32 link, respectively, responsive to determining that the UCIe x64 module supports FLW;
• means for establishing the first x32 link with the first UCIe x32 module using a plurality of mainband transmit signal lanes including a first 32 bits of a mainband data transmit signal lane, a plurality of mainband receive signal lanes including a first 32 bits of a mainband data receive signal lane, and a plurality of sideband signal lanes, responsive to determining that the UCIe x64 module is communicatively coupled to the first UCIe x32 module and the second UCIe x32 module;
• means for establishing the second x32 link with the second UCIe x32 module using a second 32 bits of the mainband data transmit signal lane, a second 32 bits of the mainband data receive signal lane, a plurality of redundant mainband transmit signal lanes, a plurality of redundant mainband receive signal lanes, and a plurality of redundant sideband signal lanes, responsive to determining that the UCIe x64 module is communicatively coupled to the first UCIe x32 module and the second UCIe x32 module;
• and
• means for establishing data transfer via the first x32 link and the second x32 link, responsive to determining that the UCIe x64 module is communicatively coupled to the first UCIe x32 module and the second UCIe x32 module.

A method for providing Flexible Link Width (FLW) dual 32-bit (x32) links in Universal Chiplet Interconnect Express (UCIe) 64-bit (x64) modules, comprising:

• determining, by a UCIe x64 module during a first initialization of a processor-based device, that the UCIe x64 module supports FLW;
• responsive to determining that the UCIe x64 module supports FLW, determining, by the UCIe x64 module during the first initialization of the processor-based device, that the UCIe x64 module is communicatively coupled to a first UCIe x32 module and a second UCIe x32 module that require a first x32 link and a second x32 link, respectively;
• and
• responsive to determining that the UCIe x64 module is communicatively coupled to the first UCIe x32 module and the second UCIe x32 module:
• establishing, by the UCIe x64 module, the first x32 link with the first UCIe x32 module using a plurality of mainband transmit signal lanes including a first 32 bits of a mainband data transmit signal lane, a plurality of mainband receive signal lanes including a first 32 bits of a mainband data receive signal lane, and a plurality of sideband signal lanes;
• establishing, by the UCIe x64 module, the second x32 link with the second UCIe x32 module using a second 32 bits of the mainband data transmit signal lane, a second 32 bits of the mainband data receive signal lane, a plurality of redundant mainband transmit signal lanes, a plurality of redundant mainband receive signal lanes, and a plurality of redundant sideband signal lanes;
• and
• establishing, by the UCIe x64 module, data transfer via the first x32 link and the second x32 link.

A non-transitory computer-readable medium, having stored thereon computer-executable instructions that, when executed by a processor device of a processor-based device, cause a Universal Chiplet Interconnect Express (UCIe) 64-bit (x64) module of the processor device to:

• determine, during a first initialization of the processor-based device, that the UCIe x64 module supports Flexible Link Width (FLW);
• responsive to determining that the UCIe x64 module supports FLW, determine, during the first initialization of the processor-based device, that the UCIe x64 module is communicatively coupled to a first UCIe 32-bit (x32) module and a second UCIe x32 module that require a first x32 link and a second x32 link, respectively;
• and
• responsive to determining that the UCIe x64 module is communicatively coupled to the first UCIe x32 module and the second UCIe x32 module:
• establish the first x32 link with the first UCIe x32 module using a plurality of mainband transmit signal lanes including a first 32 bits of a mainband data transmit signal lane, a plurality of mainband receive signal lanes including a first 32 bits of a mainband data receive signal lane, and a plurality of sideband signal lanes;
• establish the second x32 link with the second UCIe x32 module using a second 32 bits of the mainband data transmit signal lane, a second 32 bits of the mainband data receive signal lane, a plurality of redundant mainband transmit signal lanes, a plurality of redundant mainband receive signal lanes, and a plurality of redundant sideband signal lanes;
• and
• establish data transfer via the first x32 link and the second x32 link.