Back to results
US 7,136,953 B1Granted
Apparatus, system, and method for bus link width optimization
AssigneeNVIDIA Corporation
InventorsLuc R. Bisson, Oren Rubinstein, Wei-Je Huang, Michael B. Diamond
Life of this patent
Estimating the term…
Abstract
A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation.
Claims23
A method of bus power management, comprising:
- for a first operational state having a first link bandwidth requirement for a bus, negotiating a first link width between a first bus interface and a second bus interface disposed at opposite ends of said bus based on said first link bandwidth requirement, said first link width having a first integer number, M, of active data lanes that is less than or equal to a maximum integer number, K, of operable data lanes;
- and
- in response to detecting a second operational state having a second link bandwidth requirement, negotiating a second link width between said first bus interface and said second bus interface based on said second link bandwidth requirement said second link width having a second integer number, N, of active data lanes, where N is not equal to M, and N is also less than or equal to K;
- wherein the number of active data lanes that is negotiated is based on a bandwidth constraint to reduce the power consumption associated with active data lanes.
1 more element
A method of bus power management:
- detecting operable data lanes in a detect state;
- establishing common communication parameters for said data lanes in a subsequent polling state;
- entering a configuration state;
- for a first operational state having a first link bandwidth requirement, negotiating a first link width between a first bus interface at one end of a bus and a second bus interface at another end of the bus, said first link width having a first integer number, M, of active data lanes that is less than or equal to a maximum integer number, K, of operable data lanes;
- entering an operational state with said first integer number, M, of active data lanes associated as a link between bus components;
- triggering entry back into said configuration state in response to detecting a second operational state having a second link bandwidth requirement;
- negotiating a second link width between said first bus interface and said second bus interface, said second link width having a second integer number, N, of active data lanes, where N is not equal to M, and N is also less than or equal to K;
- and entering said second operational state with said second integer number, N, of active data lanes associated as said link between said bus components
- wherein the number of active data lanes that is negotiated is based on a bandwidth constraint to reduce the power consumption associated with active data lanes.
6 more elements
A data bus, comprising:
- a first data interface disposed at one end of said data bus;
- a second data interface disposed at the other end of said data bus;
- a plurality of data lanes for communicating data between said first data interface and said second data interface;
- said first data interface and said second data interface adapted to initiate a negotiation for a number of active lanes corresponding to a subset of operable data lanes;
- said first data interface and said second data interface re-negotiating the number of active data lanes to place a constraint on the number of active data lanes associated to form a link in response to a re-negotiation signal;
- wherein the number of active data lanes that is negotiated is based on a bandwidth constraint to reduce the power consumption associated with active data lanes.
3 more elements
A computing system, comprising:
- a root complex;
- a CPU coupled to the root complex for executing a software application stored in a memory;
- an endpoint device associating a graphical processing unit (GPU);
- a bus having a plurality of data lanes coupling the root complex to the endpoint device;
- the bus having bus interface disposed at two ends of the bus configured to associate active data lanes into a common link having a lane width corresponding to a number of active data lanes selected to adapt to the bandwidth requirements of the GPU;
- wherein the number of active data lanes that is negotiated is based on a bandwidth constraint to reduce the power consumption associated with active data lanes.
3 more elements
Dependencies are inferred from the claim text.