Low-latency word alignment for serdes interfaces using inline patterns

An apparatus, comprising:

• means for decoding multibit data words in a serial datastream received from a data communication link in accordance with timing provided by a bit clock signal;
• and
• means for generating a parallel clock signal configured to:
• suppress output of the parallel clock signal when the data communication link is idle for a predefined first period of time;
• and
• reestablish output of the parallel clock signal after a predefined second period of time that follows detection of a pulse on the data communication link,
• wherein the multibit data words are decoded in accordance with timing provided by the parallel clock signal.

A method for synchronizing a communication interface circuit, comprising:

• generating multibit data words by converting a serial datastream received from a data communication link in accordance with timing provided by a bit clock signal;
• dividing the bit clock signal to obtain a parallel clock signal;
• suppressing output of the parallel clock signal when the data communication link is idle for a predefined first period of time;
• reestablishing output of the parallel clock signal after a predefined second period of time that follows detection of a pulse on the data communication link;
• and
• outputting the multibit data words in accordance with timing provided by the parallel clock signal.