Back to results
US 2026/0227822 A1Published application
Computer Architecture Having Selectable, Parallel and Serial Communication Channels Between Processors and Memory
AssigneeWisconsin Alumni Research Foundation
InventorsHao Wang, Nam Sung Kim
Life of this patent
Estimating the term…
Abstract
A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application.
Claims21
1-20. (canceled)
A system, comprising:
- a first dynamic random access memory (DRAM) coupled to a parallel memory bus, the first DRAM having a first memory address range of a shared memory address space;
- a second DRAM coupled to the processor system by a serial memory bus, the second DRAM having a second memory address range different from the first memory address range of the shared memory address space;
- and
- a processor system comprising a general-purpose processor and a special-purpose processor, the processor system coupled to the first memory via the parallel memory bus and coupled to the second memory via the serial memory bus;
- wherein the processor system is configured to:
- preferentially generate and store mappings of virtual memory addresses of data words to the first memory address range or the second memory address range, the mappings including a first virtual memory address mapping of a first data word preferentially routed to the first physical memory address and a second virtual memory address mapping of a second data word preferentially routed to the second physical memory address;
- route memory accesses to the first data word to the first physical memory address over the parallel memory bus based on the stored first virtual memory address mapping;
- and
- route the memory accesses to the second data word to the second physical memory address over the serial memory bus using the second virtual memory address mapping.
6 more elements
A computer system comprising:
- a processor system comprising a general-purpose processor and a special-purpose processor;
- a first dynamic random access memory (DRAM) coupled to the processor system by a parallel memory bus, the first DRAM having a first memory address range;
- a second DRAM coupled to the processor system by a serial memory bus, the second DRAM having a second memory address range different from the first memory address range;
- and
- an operating system stored on the computer system, the operating system comprising instructions that, when executed by the processor system, configure the processor system to:
- preferentially route memory accesses through one of the parallel memory bus and the serial memory bus;
- store a mapping of a given data word to one of the first DRAM and the second DRAM according to which of the first DRAM and the second DRAM first stored the given data word;
- and
- route memory accesses for the given data word to the parallel memory bus or the serial memory bus according to the stored mapping.
6 more elements
Dependencies are inferred from the claim text.