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US 12,619,276 B2Granted
Computer architecture having selectable parallel and serial communication channels between processors and memory
AssigneeWisconsin Alumni Research Foundation
InventorsHao Wang, Nam Sung Kim
Life of this patent
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Abstract
A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application.
Claims18
An electronic computer comprising:
- a processor system having:
- (a) a first processor;
- (b) a second processor;
- an electronic memory communicating with the processor system and storing data words for reading and writing by the processor system at memory addresses, the electronic memory including a first memory bank having a first address range and a second memory bank having a second address range different from the first address range;
- a parallel bus communicating between the processor system and the first memory bank providing transmission of different bits of given data words in parallel on separate conductors of a parallel lane and not communicating with the second memory bank;
- a serial bus communicating between the processor system and the second memory bank providing transmission of different bits of given data words serially on at least one conductor of a serial lane, and not communicating with the first memory bank;
- and
- a memory access manager:
- (a) providing communication between the electronic memory and the first processor on both of the parallel bus and the serial bus;
- (b) providing communication between the electronic memory and the second processor on both of the parallel bus and the serial bus;
- (c) dynamically selecting between the parallel bus and serial bus for communication between the electronic memory and each processor of the processor system as determined by a memory address of data being communicated falling within either of the first address range or second address range,
- wherein the serial bus provides multiple lanes each providing a bit rate of memory access words through a corresponding of the at least one conductor of at least 10 Gb per second;
- and
- wherein each lane transmits bits according to an independent clock for the lane provided by an embedded clock protocol within the transmitted data of the lane.
11 more elements
An electronic computer comprising:
- a processor system having:
- (a) a first processor;
- (b) a second processor;
- an electronic memory communicating with the processor system and storing data words for reading and writing by the processor system at memory addresses, the electronic memory including a first memory bank having a first address range and a second memory bank having a second address range different from the first address range wherein the electronic memory is dynamic random-access memory;
- a parallel bus communicating between the processor system and the first memory bank providing transmission of different bits of given data words in parallel on separate conductors of a parallel lane and not communicating with the second memory bank;
- a serial bus communicating between the processor system and the second memory bank providing transmission of different bits of given data words serially on at least one conductor of a serial lane, and not communicating with the first memory bank;
- and
- a memory access manager:
- (a) providing communication between the electronic memory and the first processor on both of the parallel bus and the serial bus;
- (b) providing communication between the electronic memory and the second processor on both of the parallel bus and the serial bus;
- (c) dynamically selecting between the parallel bus and serial bus for communication between the electronic memory and each processor of the processor system as determined by a memory address of data being communicated falling within either of the first address range or second address range.
8 more elements
Dependencies are inferred from the claim text.