G06F 13/1684
Using multiple buses
Official title: {using multiple buses}
G06F13/1684 (Using multiple buses) appears on 813 US grants and 903 published applications in this corpus.
Search patents in G06F- Granted patents
- 813
- Published applications
- 903
- Assignees
- 225
- Inventors
- 1,381
- Latest grant
- 25 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 2 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 1 | 0 |
| 1991 | 1 | 0 |
| 1992 | 1 | 0 |
| 1993 | 1 | 0 |
| 1994 | 2 | 0 |
| 1995 | 1 | 0 |
| 1996 | 2 | 0 |
| 1997 | 3 | 0 |
| 1998 | 8 | 0 |
| 1999 | 2 | 0 |
| 2000 | 4 | 0 |
| 2001 | 6 | 2 |
| 2002 | 13 | 14 |
| 2003 | 14 | 13 |
| 2004 | 16 | 31 |
| 2005 | 10 | 46 |
| 2006 | 27 | 39 |
| 2007 | 34 | 35 |
| 2008 | 24 | 47 |
| 2009 | 34 | 53 |
| 2010 | 30 | 30 |
| 2011 | 40 | 39 |
| 2012 | 35 | 34 |
| 2013 | 39 | 41 |
| 2014 | 46 | 33 |
| 2015 | 28 | 32 |
| 2016 | 44 | 29 |
| 2017 | 32 | 26 |
| 2018 | 29 | 32 |
| 2019 | 35 | 43 |
| 2020 | 35 | 35 |
| 2021 | 44 | 45 |
| 2022 | 39 | 47 |
| 2023 | 39 | 29 |
| 2024 | 33 | 45 |
| 2025 | 36 | 47 |
| 2026 | 22 | 36 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Synchronous wired-or ack status for memory with variable write latency25 Aug 2026US 12,720,909 B2Rambus Inc.
- Techniques to utilize near memory compute circuitry for memory-bound workloads18 Aug 2026US 12,711,088 B2Intel Corporation
- Systems and methods for high bandwidth memory with unidirectional data flow11 Aug 2026US 12,705,202 B2Google Inc.
- Multi-stack compute chip and memory architecture21 Jul 2026US 12,688,131 B2Advanced Micro Devices, Inc.
- Interface for memory readout from a memory component in the event of fault23 Jun 2026US 12,664,107 B2Rambus Inc.
- Data storage system including interface device3 Sep 2026US 2026/0259839 A1SK hynix Inc.
- Semiconductor device and method for controlling the semiconductor device13 Aug 2026US 2026/0236420 A1Renesas Electronics Corporation
- Storage controller device configured to perform a computation, multi-chip package and computing system using the storage controller device13 Aug 2026US 2026/0236425 A1SK hynix Inc.
- Computer Architecture Having Selectable, Parallel and Serial Communication Channels Between Processors and Memory6 Aug 2026US 2026/0227822 A1Wisconsin Alumni Research Foundation
- Multi-Path Fabric Access via Translation for Non-UIO PCIe Processors, Accelerators, Switches, and Devices30 Jul 2026US 2026/0220069 A1UnifabriX Ltd.
Most cited
By later US patents
- Memory system including a point-to-point linked memory subsystem431US 6,502,161 B1Rambus Inc. · 2002
- Memory system controller to manage wear leveling across a plurality of storage nodes339US 8,412,880 B2Micron Technology, Inc. · 2013
- Source-clock-synchronized memory system and memory unit323US 6,034,878 AHitachi, Ltd. · 2000
- Multi-tier point-to-point ring memory interface283US 6,658,509 B1Intel Corporation · 2003
- Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing229US 6,625,687 B1Intel Corporation · 2003