Synchronous wired-or ack status for memory with variable write latency
AssigneeRambus Inc.
InventorsYohan Frans, Simon Li, John Eric Linstadt, Jun Kim
Life of this patent
Estimating the term…
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AssigneeRambus Inc.
InventorsYohan Frans, Simon Li, John Eric Linstadt, Jun Kim
Estimating the term…
A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.
A memory device comprising:
A method of operating a memory device, the method comprising:
A memory device comprising:
Dependencies are inferred from the claim text.