Multi-Path Fabric Access via Translation for Non-UIO PCIe Processors, Accelerators, Switches, and Devices

A system for enabling multi-path routing for a requester, comprising:

• a first interface configured to communicate with a first entity that does not utilize Unordered Input/Output (UIO);
• a second interface configured to communicate with one or more second entities via a path supporting multi-path routing;
• and
• a computer coupled between the first interface and the second interface, the computer configured to:
• receive, via the first interface, a Peripheral Component Interconnect Express (PCIe) memory request from the first entity;
• translate the PCIe memory request to a PCIe UIO memory request;
• send, via the second interface, the PCIe UIO memory request to at least one of the second entities;
• receive, via the second interface, a PCIe UIO Completion from the at least one of the second entities;
• translate the PCIe UIO Completion to a PCIe non-UIO Completion;
• and
• send, via the first interface, the PCIe non-UIO Completion to the first entity.

A method for managing ordering in translation, comprising:

• receiving, from a first entity, a Peripheral Component Interconnect Express (PCIe) Unordered Input/Output (UIO) memory request, wherein the first entity is configured to enforce ordering requirements for the PCIe UIO memory request;
• translating, by a computer, the PCIe UIO memory request to a PCIe non-UIO memory request;
• sending the PCIe non-UIO memory request to a second entity via a path that enforces fabric-based ordering;
• receiving, from the second entity, a PCIe non-UIO Completion;
• translating, by the computer, the PCIe non-UIO Completion to a PCIe UIO Completion;
• and
• sending the PCIe UIO Completion to the first entity.

A system for managing ordering in translations, comprising:

• a first interface configured to communicate with a first entity that utilizes Peripheral Component Interconnect Express (PCIe) Unordered Input/Output (UIO) and is configured to enforce ordering requirements;
• a second interface configured to communicate with a second entity via a path that enforces fabric-based ordering;
• and
• a computer coupled between the first interface and the second interface, the computer configured to:
• receive, via the first interface, a PCIe UIO memory request from the first entity;
• translate the PCIe UIO memory request to a PCIe non-UIO memory request;
• send, via the second interface, the PCIe non-UIO memory request to the second entity;
• receive, via the second interface, a PCIe non-UIO Completion from the second entity;
• translate the PCIe non-UIO Completion to a PCIe UIO Completion;
• and
• send, via the first interface, the PCIe UIO Completion to the first entity.