Memory system including a point-to-point linked memory subsystem
AssigneeRambus Inc.
InventorsRichard E. Perego, Stefanos Sidiropoulos, Ely Tsern
Life of this patent
Estimating the term…
Abstract
A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link.
Claims49
A memory system comprising:
- a memory controller having an interface that includes a plurality of memory subsystem ports;
- a first memory subsystem including:
- a buffer device having a first port and a second port, and
- a plurality of memory devices coupled to the buffer device via the second port, wherein data is transferred between at least one memory device of the plurality of memory devices and the memory controller via the buffer device;
- and
- a plurality of point-to-point links, each point-to-point link of the plurality of point-to-point links having a connection to a respective memory subsystem port of the plurality of memory subsystem ports, the plurality of point-to-point links including a first point-to-point link to connect the first port to a first memory subsystem port of the plurality of memory subsystem ports.
A memory system comprising:
- a controller device;
- a first buffer device having a first interface and a second interface;
- a second buffer device having a first interface and a second interface;
- a first point-to-point link having a first connection to the controller device and a second connection to the first interface of the first buffer device;
- a first plurality of memory devices connected to the second interface of the first buffer device;
- a second point-to-point link having a first connection to the controller device and a second connection to the first interface of the second buffer device;
- and
- a second plurality of memory devices connected to the second interface of the second buffer device.
A memory system comprising:
- a controller device;
- a first and second plurality of buffer devices, each buffer device of the first and second plurality of buffer devices having an interface connected to a respective plurality of memory devices;
- a first and second repeater device;
- a first point-to-point link having a first connection to the controller device and a second connection to the first repeater device;
- a second point-to-point link having a first connection to the controller device and a second connection to the second repeater device;
- a first plurality of repeater links, each repeater link having first connection to a respective buffer device of the first plurality of buffer devices, and a second connection to the first repeater device;
- and
- a second plurality of repeater links, each repeater link having first connection to a respective buffer device of the second plurality of buffer devices and a second connection to the second repeater device.
A memory system comprising:
- a controller device having an interface;
- a first connector, second connector, and third connector;
- a first point-to point link having a first connection to the interface and a second connection to the first connector;
- a second point-to-point link having a first connection to the interface and a second connection to the second connector;
- a third point-to-point link having a first connection to the interface and a second connection to the third connector;
- and
- a first memory subsystem including:
- a buffer device connected to the first connector;
- and
- a plurality of memory devices connected to buffer device, wherein at least one memory device of the plurality of memory devices transfer data to the controller device via the buffer device.
The memory device of claim wherein the buffer device further includes a write buffer to hold data to be provided to at least one memory device of the plurality of memory devices.
Dependencies are inferred from the claim text.