Interface for memory readout from a memory component in the event of fault
AssigneeRambus Inc.
InventorsFrederick A. Ware, Kenneth L. Wright
Life of this patent
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Abstract
Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.
Claims20
A memory device, comprising:
- memory core circuitry to store data;
- a primary interface including a data interface for coupling to multiple data paths and a command/address (C/A) interface for coupling to a command/address path, the primary interface to provide access to the data stored in the memory core circuitry during a normal mode of operation;
- and
- a secondary interface that is independent from the primary interface, the secondary interface to receive offloaded data from a second memory device during a fault mode of operation.
An integrated circuit (IC) dynamic random access memory (DRAM) device, comprising:
- memory core circuitry to store data;
- a parallel interface including a data interface for coupling to multiple data paths and a command/address (C/A) interface for coupling to a command/address path, the parallel interface to provide access to the data stored in the memory core circuitry during a normal mode of operation;
- and
- a serial interface that is independent from the parallel interface, the serial interface to receive offloaded data from a second memory device during a fault mode of operation.
A method of operating an integrated circuit (IC) memory device, comprising
- providing access, via a parallel interface, to data stored in memory core circuitry during a normal mode of operation, the parallel interface including a data interface for coupling to multiple data paths and a command/address (C/A) interface for coupling to a command/address path;
- and
- receiving offloaded data from a second IC memory device via a serial interface during a fault mode of operation, the serial interface being independent from the parallel interface.
Dependencies are inferred from the claim text.