Multi-tier point-to-point ring memory interface

A memory module comprising:

• at least one bank of memory devices;
• a module controller to communicate memory signals with the bank of memory devices over a memory module bus, the module controller capable of connecting to a primary memory controller along a ring bus, the module controller comprising an interface circuit to transfer memory signals between the memory module bus and the ring bus,
• wherein the module controller is capable of communication with the primary memory controller to send a set of data signals between the two, by sending one portion of the set of data signals in a clockwise direction on the first ring bus and sending the remainder of the set of data signals in a counterclockwise direction on the first ring bus.

A memory module comprising:

• at least two banks of memory devices, each bank having first and second level-two ports;
• a module controller, having first and second level-two ports, connected with the memory device banks in a module ring bus, wherein each of the memory device banks and the controller are capable of transmitting memory signals in a clockwise direction on the module ring bus using the corresponding first level-two port, and in a counterclockwise direction on the module ring bus using the corresponding second level-two port, and wherein each memory device bank is capable of retransmitting memory signals received by that bank at one level-two port on the other level-two port.

A method of host/memory communication comprising:

• transmitting a partial set of memory signals over a clockwise bus path between a first-tier controller and a selected one of a plurality of memory units, wherein the first-tier controller and the plurality of memory units are linked by a first ring memory bus, wherein each of the memory units and the controller are capable of transmitting memory signals in a clockwise direction and in a counterclockwise direction on the bus, and wherein each memory unit is capable of retransmitting memory signals received on the bus along the bus;
• and
• transmitting the remainder of the set of memory signals over a counterclockwise bus path between the controller and the selected memory unit.