Techniques to utilize near memory compute circuitry for memory-bound workloads

A method comprising:

• receiving a request at first circuitry resident on an input/output (I/O) switch that is arranged to couple with a plurality of memory devices configured in a first memory pool and a second portion of the plurality of memory devices configured in a second memory pool, the first and second memory pools accessible to one or more host central processing units (CPUs) through the I/O switch, wherein the I/O switch also has a first memory controller to enable the first circuitry to access the first memory pool and also includes a second circuitry and a second memory controller resident on the I/O switch, the second memory controller to enable the second circuitry to access the second memory pool, and wherein the request is received from a first host CPU for obtaining data from the first memory pool and for processing the obtained data;
• obtaining, by the first circuitry, the data from the first memory pool based on memory address information included in the request from the first host CPU;
• processing, by the first circuitry, the data to generate a result for the first host CPU;
• and
• cause, by the first circuitry, the result for the first host CPU to be stored to a memory accessible to the first host CPU.