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US 12,688,131 B2Granted
Multi-stack compute chip and memory architecture
AssigneeAdvanced Micro Devices, Inc.
InventorsMichael Ignatowski, Michael J. Schulte, Gabriel Hsiuwei Loh
Life of this patent
Estimating the term…
Abstract
Multi-stack compute chip and memory architecture is described. In accordance with the described techniques, a package includes a plurality of computing stacks, and each computing stack includes at least one compute chip and a memory. The package also includes one or more interconnects that couple the computing stacks to at least one other computing stack for sharing the memory in a coherent fashion across the plurality of computing stacks.
Claims46
An apparatus comprising:
- a package including:
- a plurality of computing stacks integrated within the package, wherein a first computing stack and a second computing stack of the plurality of computing stacks each include at least one compute chip and memory, wherein the at least one compute chip is configured to access data in the memory of at least one of the first computing stack or the second computing stack to execute instructions of a program;
- and
- one or more interconnects of the package that couple the first computing stack to at least the second computing stack for sharing the memory.
1 more element
A system on package (SoP) comprising:
- a plurality of computing stacks integral with a substrate of a package, wherein:
- each computing stack of the plurality of computing stacks includes at least one compute chip coupled to one or more memory dies;
- and
- at least a first computing stack of the plurality of computing stacks is coupled to at least a second computing stack and a third computing stack of the plurality of computing stacks via interconnects for sharing the one or more memory dies, wherein the at least one compute chip is configured to access data in the one or more memory dies of at least one of the first computing stack or the second computing stack to execute instructions of a program;
- and
- one or more interfaces of the package to couple the package to at least one external device.
3 more elements
A method for fabricating a multi-stack package comprising:
- forming a plurality of computing stacks, wherein a first computing stack and a second computing stack of the plurality of computing stacks each include at least one compute chip and memory, wherein the at least one compute chip is configured to access data in the memory of at least one of the first computing stack or the second computing stack to execute instructions of a program;
- and
- disposing the plurality of computing stacks on a substrate of a package, the first computing stack and the second computing stack being electrically connected on the substrate via one or more interconnects for sharing the memory.
Dependencies are inferred from the claim text.