Source-clock-synchronized memory system and memory unit

A source-clock-synchronized memory system for use in apparatus which includes a base board and a memory controller provided on said base board, said source-clock-synchronized memory comprising:

• a memory unit for mounting on said base board,
• wherein said memory unit comprises:
• a memory riser board mounted on said base board through at least a connector, said memory riser board being provided with a plurality of front memory modules mounted on the front surface of said memory riser board and a plurality of back memory modules mounted on the back surface of said memory riser board,
• wherein signal lines including address/command and data lines, each being accompanied by a clock signal line, start from said memory controller, pass through said connector, are wired to said front memory modules mounted on said front surface of said first memory riser board sequentially one module after another, pass through the top of said memory riser board and are wired to said back memory modules mounted on said back surface of said memory riser board sequentially one module after another;
• and
• wherein at least said data line further passes through said connector and is connected back to said memory controller in a ring state.

A source-clock-synchronized memory system for use in apparatus which includes a base board, and a memory controller provided on said base board, said source-clock-synchronized memory system comprising:

• a memory unit provided on said base board,
• wherein said memory unit comprises:
• a memory riser board mounted on said base board through at least a connector with a plurality of memory modules mounted on the front and back surfaces of said memory riser board, and
• a switch for connecting a data line wired to said connector to one of two data lines wired to said modules in accordance with a control signal output by said memory controller;
• wherein signal lines including address/command lines, each being accompanied by a clock signal line, start from said memory controller, pass through said connector and are wired to said memory modules mounted on the front and back surfaces of said memory riser board sequentially one module after another;
• and
• wherein a data line including said data line wired to said connector and said two data lines wired to said memory modules starts from said memory controller, passes through said connector and said switch, is wired to said memory modules mounted on the front and back surfaces of said memory riser board sequentially one module after another, passes through said switch again and is folded back to said memory controller, said data lines passing to each of said modules from said memory controller in a ring state.

A memory unit for use in apparatus which includes a base board and a memory controller provided on said base board, said memory unit comprising:

• a first memory riser board mounted on said base board through a first connector with a plurality of first memory modules mounted on the front surface of said first memory riser board;
• a second memory riser board mounted on said base board through a second connector with a plurality of second memory modules mounted on the front surface of said second memory riser board,
• wherein said first and second memory riser boards are arranged such that the back surface of said first memory riser board faces the back surface of said second memory riser board;
• and
• a board linking connector for connecting signal lines on said first memory riser board to corresponding signal lines on said second memory riser board,
• wherein said signal lines address/command and data lines, each being accompanied by a clock signal line, start from contact points on said first connector, are wired to said first memory modules mounted on said first memory riser board sequentially one module after another, pass through said board linking connector and are wired to said second memory modules mounted on said second memory riser board sequentially one module after another, said data lines passing to each of said modules from said memory controller in a ring state, and
• wherein at least said data line is further extended to another contact point on said second connector.

A memory unit for use in apparatus which includes a base board and a memory controller provided on said base board, said memory unit comprising:

• a memory riser board mounted on said base board through at least a connector with a plurality of front memory modules mounted on the front surface of said memory riser board and a plurality of back memory modules mounted on the back surface of said memory riser board;
• and
• a plurality of signal lines including address/command and data lines, each being accompanied by a clock signal line, said signal lines start from contact points on said connector, are wired to said front memory modules mounted on said front surface of said first memory riser board sequentially one module after another, pass through the top of said memory riser board and are wired to said back memory modules mounted on said back surface of said memory riser board sequentially one module after another, said data lines passing to each of said modules from said memory controller in a ring state,
• wherein at least said data line is further extended to another contact point on said connector.

A connector for removably mounting a memory unit which includes a memory riser board having a plurality of memory modules mounted on the front surface thereof, on a base board apparatus so as to connect signal lines on said memory unit to signal-line wires on said base board, said connector comprising:

• a connector box having an accepting mouth for accepting and firmly holding said memory riser board of said memory unit, wherein a shape of said accepting mouth corresponds to a cross section of said memory riser board;
• a first pin connected to one of said signal-line wires on said base board and extended from said base board to said accepting mouth;
• and
• a second pin connected to another of said separated signal-line wires on said base board and extended from said base board to said accepting mouth,
• wherein, when said memory riser board is not mounted, said first pin comes in contact with said second pin, electrically connecting signal-line wires connected to said pins to each other and when said memory riser board is mounted said first pin comes in contact with a signal line on the front surface of said memory riser board, electrically connecting said first pin to said signal line on said front surface whereas said second pin comes in contact with a signal line on the back surface of said memory riser board, electrically connecting said second pin to said signal line on said back surface.

An information processing system comprising:

• a base board;
• a memory controller provided on said base board;
• and
• a memory unit mounted on said base board for storing information under control of said memory controller,
• wherein said memory unit comprises:
• a first memory riser board mounted on said base board through a first connector with a plurality of first memory modules mounted on the front surface of said first memory riser board,
• a second memory riser board mounted on said base board through a second connector with a plurality of second memory modules mounted on the front surface of said second memory riser board,
• wherein said first and second memory riser boards are arranged such that the back surface of said first memory riser board faces the back surface of said second memory riser board, and
• a board linking connector for connecting signal lines on said first memory riser board to corresponding signal lines on said second memory riser board,
• wherein said signal lines include address/command and data lines, each being accompanied by a clock signal line, that start from said memory controller, path through said first connector, are wires to said first memory modules mounted on said first memory riser board sequentially one module after another, pass through said board making connector and are wired to said second memory modules mounted on said second memory riser board sequentially one module after another, and
• wherein at least said data line further passes through said second connector and is mounted back to said memory controller in a ring state.

An information processing system, comprising:

• a base board;
• a memory controller provided on said base board;
• and
• a memory unit mounted on said base board for storing data under control of said memory controller,
• wherein said memory unit comprises:
• a memory riser board mounted on said base board through at least a connector, said memory riser board being provided with a plurality of front memory modules mounted on the front surface of said memory riser board and a plurality of back memory modules mounted on the back surface of said memory riser board,
• wherein signal lines including address/command and data lines, each being accompanied by a clock signal line, start from said memory controller, pass through said connector, are wired to said front memory modules mounted on said front surface of said first memory riser board sequentially one module after another, pass through the top of said memory riser board and are wired to said back memory modules mounted on said back surface of said memory riser board sequentially one module after another;
• and
• wherein at least said data line further passes through said connector and is connected back to said memory controller in a ring state.

An information processing system, comprising:

• a base board;
• a memory controller provided on said base board;
• and
• a memory unit mounted on said base board for storing data under control of said memory controller,
• wherein said memory unit comprises:
• a memory riser board mounted on said base board through at least a connector with a plurality of memory modules mounted on the front and back surfaces of said memory riser board, and
• a switch for connecting a data line wired to said connector to one of two data lines wired to said modules in accordance with a control signal output by said memory controller;
• wherein signal lines including address/command lines, each being accompanied by a clock signal line, start from said memory controller, pass through said connector and are wired to said memory modules mounted on the front and back surfaces of said memory riser board sequentially one module after another;
• and
• wherein a data line including said data line wired to said connector and said two data lines wired to said memory modules starts from said memory controller, passes through said connector and said switch, is wired to said memory modules mounted on the front and back surfaces of said memory riser board sequentially one module after another, passes through said switch again and is folded back to said memory controller, said data lines passing to each of said modules from said memory controller in a ring state.