Y10S 148/156
Sonos
Y10S148/156 (Sonos) appears on 9 US grants and 0 published applications in this corpus.
Search patents in Y10S- Granted patents
- 9
- Published applications
- 0
- Assignees
- 8
- Inventors
- 10
- Latest grant
- 25 Oct 1994
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 1 | 0 |
| 1980 | 1 | 0 |
| 1981 | 1 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 3 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 1 | 0 |
By publication year. Applications have been published since 2001.
Recent patents
- Etch stop useful in avoiding substrate pitting with poly buffered locos25 Oct 1994US 5,358,892 AMicron Semiconductor, Inc.
- Method for manufacturing a semiconductor device utilizing self-aligned contact regions16 May 1989US 4,830,971 ATokyo Shibaura Denki Kabushiki Kaisha
- Method for manufacturing a semiconductor device utilizing self-aligned silicide regions18 Nov 1986US 4,622,735 ATokyo Shibaura Denki Kabushiki Kaisha
- Method of manufacturing a semiconductor device with a stacked-gate-electrode structure14 Oct 1986US 4,616,402 AKabushiki Kaisha Toshiba
- Process for high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines13 May 1986US 4,587,711 ARockwell International Corporation
No published applications in this class yet.
Most cited
By later US patents
- Process for producing an integrated multi-layer insulator memory cell114US 4,257,832 ASiemens Aktiengesellschaft · 1981
- Method for manufacturing a semiconductor device utilizing self-aligned silicide regions71US 4,622,735 ATokyo Shibaura Denki Kabushiki Kaisha · 1986
- Gate electrode for MNOS semiconductor memory device37US 4,151,537 AGTE Laboratories Incorporated · 1979
- Method of manufacturing a semiconductor device with a stacked-gate-electrode structure33US 4,616,402 AKabushiki Kaisha Toshiba · 1986
- Method for manufacturing a semiconductor device utilizing self-aligned contact regions28US 4,830,971 ATokyo Shibaura Denki Kabushiki Kaisha · 1989