Process for producing an integrated multi-layer insulator memory cell
AssigneeSiemens Aktiengesellschaft
InventorsUlrich Schwabe, Erwin Jacobs
Life of this patent
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Abstract
An integrated multi-layer insulator memory cell is produced via silicon-gate technology, with self-adjusting, overlapping polysilicon contact wherein a gate oxide of a peripheral transistor is produced after the application of multi-layer insulating layer comprised of a storage layer and a "blocking" layer. The "blocking" layer consists of an oxynitride layer formed by oxidation of a silicon nitride layer surface or an additionally applied SiO.sub.2 layer and has a layer thickness of about 5 to 30 nm. Such "blocking" layer prevents an undesired injection of charge carriers from the silicon-gate electrode. It also provides means for forming a self-adjusting, overlapping polysilicon contact.
Claims9
A process for producing an integrated multi-insulator memory cell with a self-adjusting overlying polysilicon contact using silicon gate technology comprising applying a relatively thin SiO.sub.2 layer having a thickness of about 1.5 to 12 nm onto the semiconductor substrate and applying an oxynitride layer of a composition (Si.sub.x O.sub.y N.sub.z) wherein x, y and z are integers having a thickness of about 20 to 60 nm above said SiO.sub.2 layer with said SiO.sub.2 layer functioning as a tunnel oxide and said oxynitride layer functioning as a storage layer, and wherein a gate oxide layer having a thickness of about 50 to 100 nm is produced by a further oxidation of said substrate.
A process for producing an integrated multi-layer insulator memory cell with a self-adjusting, overlying polysilicon contact using silicon gate technology comprising applying a multi-layer insulator comprising a relatively thin SiO.sub.2 layer having a thickness of about 1.5 to 12 nm onto the surface of the semiconductor substrate and applying at selected locations onto the relatively thin silicon dioxide layer, a silicon nitride layer having a thickness of about 20 to 60 nm wherein said thin silicon dioxide layer functions as a tunnel oxide and said silicon nitride layer functions as a storage layer, producing a gate oxide layer having a thickness of 50 to 100 nm by further oxidation of said substrate, and substantially simultaneously forming an oxynitride layer having a thickness of about 5 to 30 nm by oxidation of said silicon nitride layer and said oxynitride layer functioning as a blocking layer.
A process for producing an integrated multi-layer insulator memory cell with a self-adjusting, overlapping polysilicon contact using silicon-gate technology, comprising, in combination, the sequential steps:
- (a) producing a structured SiO.sub.2 layer on a semiconductor substrate for separation of active transistor zones from one another according to the LOCOS-process;
- (b) oxidizing the entire substrate surface with a relatively thin SiO.sub.2 layer, which functions as a tunnel oxide,
- (c) producing a structured silicon nitride layer in the region of a storage transistor and producing an overlapping contact;
- (d) applying a gate oxide layer using oxidation and substantially simultaneously transforming the surface of the silicon nitride layer into an oxynitride layer, which functions as a blocking layer;
- (e) depositing a polysilicon layer onto the entire substrate surface and thereafter structuring such polysilicon layer;
- (f) producing source-drain zones in said substrate;
- (g) depositing a silicon dioxide layer over the entire substrate surface and thereafter structuring such silicon dioxide layer so as to function as an intermediate oxide;
- (h) producing contact holes to the source-drain zones and to the polysilicon layer above the thick oxide zone in said substrate;
- and
- (i) depositing metal over the entire surface of said substrate and thereafter structuring such metal layer into contacts.
Dependencies are inferred from the claim text.