US 4,616,402 AGranted

Method of manufacturing a semiconductor device with a stacked-gate-electrode structure

AssigneeKabushiki Kaisha Toshiba

InventorSeiichi Mori

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Abstract

A method of manufacturing a semiconductor device with a stacked-gate-electrode structure which includes; forming source and drain regions in the surface portion of a semiconductor substrate in a spaced-apart relationship, forming a floating gate such that it overlies the channel region between the source and drain regions with a gate insulating film therebetween, and forming a control gate such that it overlies the floating gate with an insulating film therebetween. An oxidation-resistant film pattern having a predetermined opening is formed over a non-monocrystalline silicon layer. The non-monocrystalline silicon layer within the opening is selectively oxidized with the oxidation-resistant film pattern as a mask to form a separation insulating film. In this way, a floating gate layer is formed with the portion of the non-monocrystalline silicon layer insulatingly separated. With the oxidation-resistant film pattern left over the floating gate layer and with the separation insulating film left within the opening, a control gate layer is formed over the surface of the resultant surface to permit the whole surface of the resultant surface to be planarized.

Claims14

Dependent claims

A method of manufacturing a semiconductor device with a stacked-gate-electrode structure, comprising the steps of:

forming an element separation area in the surface portion of a semiconductor substrate;
forming a gate insulating film on an island region of said semiconductor substrate surrounded by the element separation area;
forming a non-monocrystalline silicon layer on the whole surface of the resultant structure;
forming over the non-monocrystalline silicon layer an oxidation-resistant film pattern having an opening at a portion thereof corresponding to a portion of the element separation area, an area of said opening being smaller than that of said portion of the element separation area;
forming a first gate electrode by selectively oxidizing a non-monocrystalline silicon layer within the opening with the oxidation-resistant film pattern as a mask to form a separation insulating film with a portion of the non-monocrystalline silicon layer insulatingly separated;
and
forming, with said oxidation-resistant film pattern left over the first gate electrode and with said separation insulating film left within the opening, a second gate electrode over the surface of the resultant structure to permit the whole surface of the resultant structure to be planarized.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 06/729,660Filed 2 May 1985
Priority: JP 59-904147 May 1984
Granted: 14 Oct 1986
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 30/681
Floating-gate IGFETs: having only two programming levels
H10D 64/035
Of data-storage electrodes: comprising conductor-insulator-conductor-insulator-semiconductor structures
H10W 10/011
Manufacture or treatment: of isolation regions comprising dielectric materials
H10W 10/10
Isolation regions in semiconductor bodies between components of integrated devices: isolation regions comprising dielectric materials