Method for manufacturing a semiconductor device utilizing self-aligned contact regions
AssigneeTokyo Shibaura Denki Kabushiki Kaisha
InventorTadashi Shibata
Life of this patent
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Abstract
A method for manufacturing a semiconductor device of the invention comprises the steps of (a) forming a gate insulating film on a surface of a silicon substrate, and a gate electrode on said gate insulating film; (b) forming a source region and a drain region by doping said substrate with an impurity which has a conductivity type opposite to a conductivity type of said silicon substrate; (c) forming a self-aligned insulating layer on the side walls of the gate electrode; (d) forming a self-aligned metal layer on a region on which an insulating film is not formed, the region including the source region and the drain region; and (e) forming electrodes which are connected to the source region, drain region and gate electrode.
Claims9
A method for manufactoring a semiconductor device, comprising the steps of:
- (a) forming a gate insulating film on a surface of a silicon substrate, and a gate electrode on said gate insulation film;
- (b) forming a source region and a drain region by doping said substrate with an impurity which has a conductivity type opposite to a conductivity type of said silicon substrate;
- (c) forming an insulating layer on said substrate and etching the insulating layer by an anistropic etching thus leaving the self-aligned insulating layer on the side walls of said gate electrode;
- (d) forming a self-aligned metal layer on a region on which an insulating film is not formed, said region including said source region and said drain region;
- and
- (e) forming electrodes which are connected to the source region,drain region and gate electrode.
A method for manufactoring a semiconductor device, comprising the steps of:
- (a) forming a gate insulating film on a surface of a silicon substrate, and a gate electrode on said gate insulation film;
- (b) forming a source region and a drain region by doping said substrate with an impurity which has a conductivity type opposite to a conductivity type of said silicon substrate;
- (c) forming an insulating layer on said substrate and etching the insulating layer by an anistropic etching thus leaving the self-aligned insulating layer on the side walls of said gate electrode;
- (d) forming a self-aligned metal silicide layer on a region on which an insulating film is not formed, said region including said source region and said drain region;
- and
- (e) forming electrodes which are connected to the source region, drain region and gate electrode.
Dependencies are inferred from the claim text.