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  1. Technology classes
  2. /H · Electricity
  3. /H10 · Semiconductor devices
  4. /H10P · Generic processes or apparatus for the manufacture or treatment of devices covered
  5. /H10P 54/00 · Cutting or separating of wafers, substrates or parts of devices
  6. /H10P 54/90 · Auxiliary processes or arrangements
  7. /H10P 54/92 · For protecting or reinforcing the surface of wafers or substrates during cutting
  8. /H10P 54/922
H10P 54/922

Arrangements for stress mitigation

Official title: {Arrangements for stress mitigation, e.g. crack stops}

H10P54/922 (Arrangements for stress mitigation) appears on 3 US grants and 9 published applications in this corpus.

Search patents in H10P

Where it sits

  1. HElectricity
  2. H10Semiconductor devices
  3. H10PGeneric processes or apparatus for the manufacture or treatment of devices covered
  4. H10P 54/00Cutting or separating of wafers, substrates or parts of devices
  5. H10P 54/90Auxiliary processes or arrangements
  6. H10P 54/92For protecting or reinforcing the surface of wafers or substrates during cutting
  7. H10P 54/922Arrangements for stress mitigation
Granted patents
3
Published applications
9
Assignees
8
Inventors
27
Latest grant
29 Sep 2026

Filings by year

Granted patentsPublished applications
H10P 54/922: granted patents and published applications per publication year
YearGranted patentsPublished applications
201801
201900
202011
202110
202200
202301
202401
202501
202614

201820192020202120222023202420252026

By publication year. 2026 runs to 8 Oct.

Recent patents

  • Edge structure of semiconductor wafer and manufacturing method thereof29 Sep 2026US 12,751,231 B2United Microelectronics Corp.
  • Semiconductor device8 Jun 2021US 11,031,357 B2Mitsubishi Electric Corporation
  • Semiconductor device25 Aug 2020US 10,756,029 B2Mitsubishi Electric Corporation
  • Method for manufacturing semiconductor device24 Sep 2026US 2026/0293564 A1Kabushiki Kaisha Toshiba
  • Semiconductor device13 Aug 2026US 2026/0239992 A1SK hynix Inc.
  • Wire electrical discharge machining apparatus, wire electrical discharge machining method, and wafer manufacturing method16 Jul 2026US 2026/0199995 A1Mitsubishi Electric Corporation
  • Sidewall padding for a semiconductor die for stress absorption and methods of forming the same16 Apr 2026US 2026/0107827 A1Taiwan Semiconductor Manufacturing Company.Ltd
  • Edge structure of semiconductor wafer and manufacturing method thereof22 May 2025US 2025/0166997 A1United Microelectronics Corp.

Most cited

By later US patents

No patent in this class has been cited by a later US patent yet.

Top assignees

Documents
  • Mitsubishi Electric Corporation5
  • United Microelectronics Corp.2
  • Apple Inc.1
  • CMChangxin Memory Technologies, Inc.1
  • Kabushiki Kaisha Toshiba1
  • SK hynix Inc.1
  • TSTaiwan Semiconductor Manufacturing Company.Ltd1
  • TEToshiba Electronic Devices & Storage Corporation1

Often classified with

  • H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by11
  • H10DInorganic electric semiconductor devices4
  • B23HWorking of metal by the action of a high concentration of electric1

Documents that also carry the other class.

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© 2026 patentgrepData from USPTO bulk files