H03K 5/1506
With parallel driven output stages
Official title: {with parallel driven output stages; with synchronously driven series connected output stages}
H03K5/1506 (With parallel driven output stages) appears on 373 US grants and 239 published applications in this corpus.
Search patents in H03K- Granted patents
- 373
- Published applications
- 239
- Assignees
- 197
- Inventors
- 717
- Latest grant
- 8 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 2 | 0 |
| 1977 | 2 | 0 |
| 1978 | 6 | 0 |
| 1979 | 3 | 0 |
| 1980 | 1 | 0 |
| 1981 | 2 | 0 |
| 1982 | 5 | 0 |
| 1983 | 1 | 0 |
| 1984 | 1 | 0 |
| 1985 | 6 | 0 |
| 1986 | 4 | 0 |
| 1987 | 10 | 0 |
| 1988 | 1 | 0 |
| 1989 | 10 | 0 |
| 1990 | 4 | 0 |
| 1991 | 6 | 0 |
| 1992 | 6 | 0 |
| 1993 | 8 | 0 |
| 1994 | 6 | 0 |
| 1995 | 9 | 0 |
| 1996 | 10 | 0 |
| 1997 | 4 | 0 |
| 1998 | 7 | 0 |
| 1999 | 4 | 0 |
| 2000 | 2 | 0 |
| 2001 | 5 | 1 |
| 2002 | 3 | 5 |
| 2003 | 10 | 11 |
| 2004 | 8 | 13 |
| 2005 | 9 | 10 |
| 2006 | 15 | 7 |
| 2007 | 8 | 8 |
| 2008 | 8 | 5 |
| 2009 | 5 | 9 |
| 2010 | 12 | 12 |
| 2011 | 9 | 10 |
| 2012 | 7 | 7 |
| 2013 | 11 | 7 |
| 2014 | 11 | 7 |
| 2015 | 5 | 9 |
| 2016 | 9 | 11 |
| 2017 | 13 | 18 |
| 2018 | 19 | 17 |
| 2019 | 26 | 13 |
| 2020 | 14 | 4 |
| 2021 | 6 | 9 |
| 2022 | 5 | 10 |
| 2023 | 11 | 12 |
| 2024 | 10 | 7 |
| 2025 | 10 | 12 |
| 2026 | 4 | 5 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Low-jitter random clock generation circuit8 Sep 2026US 12,732,176 B2Chongqing GigaChip Technology Co., Ltd.
- Multi-phase signal generation scheme and method thereof18 Aug 2026US 12,712,555 B2Intel Corporation
- Clock transmission circuit, imaging element, and method for manufacturing clock transmission circuit14 Apr 2026US 12,604,116 B2Hamamatsu Photonics K.K.
- Reducing the time to switch between the redundant clock signals applied to a phase lock loop3 Feb 2026US 12,542,547 B2International Business Machines Corporation
- Apparatus and method for monitoring duty cycle of memory clock signal25 Nov 2025US 12,483,230 B2Electronics and Telecommunications Research Institute
- Symmetric high-speed quadrature divider with feedforward path and sub-rate phase detection24 Sep 2026US 2026/0291480 A1Alphawave IP Inc.
- Radiation-hardened circuit having a feedback structure and semiconductor device including the same13 Aug 2026US 2026/0238211 A1Iucf-Hyu (Industry-University Cooperation Foundation Hanyang University)
- Clock control circuit, memory, and clock control method7 May 2026US 2026/0128080 A1CXMT Corporation
- Topological structure for ip core, and ip core19 Feb 2026US 2026/0052769 A1
- Tuning of data interface timing between clock domains5 Feb 2026US 2026/0039284 A1Texas Instruments Incorporated
Most cited
By later US patents
- Skew-free clock signal distribution network in a microprocessor172US 5,307,381 AIntel Corporation · 1994
- Circuit for determining clock propagation delay in a transmission line126US 6,219,384 B12001
- Adaptive body bias for clock skew compensation119US 7,015,741 B2Intel Corporation · 2006
- Integrated logic circuit with clock skew adjusters110US 5,122,679 AHitachi, Ltd. · 1992
- Clock signal duty cycle correction circuit and method102US 5,757,218 AInternational Business Machines Corporation · 1998