A clock distribution circuit for achieving simultaneous arrival of clock timing events at a plurality of digital subsystems, comprising:
- a source of said clock timing events having a plurality of output points, each of said output points being effective for supplying a copy of said clock timing events, said output points connected to a clock distribution network, said clock distribution network consisting of a plurality of transmission lines, each of said transmission lines being coupled via a corresponding first variable delay element to said source of said clock timing events at only a corresponding one of said plurality of output points, each of said plurality of digital subsystems being coupled to a single one of said transmission lines to receive said clock timing events therefrom, said transmission lines being terminated at said digital subsystems with an impedance at least partially reflective of said clock timing events and effective for producing a reflection signal back along said transmission line;
- a plurality of current mirrors for sensing a flow of current in each of said plurality of transmission lines, each of said current mirrors being coupled to a corresponding one of said transmission lines and having a current sensing element for sensing current flow in said transmission line and producing an activation signal in response to said current flow, a first current source responsive to said activation signal for producing a charging current output, and a second current source responsive to said activation signal for producing a discharging current output, said charging current output and discharging current output being proportional to the flow of current in said corresponding transmission line;
- a plurality of time measuring sub-circuits coupled to said plurality of current mirrors for determining a current flow time during which current flows in each of said transmission lines as sensed by said current mirrors, said current flow time being a measure of the propagation time of said clock timing events through each of said transmission lines from said variable delay elements to said digital subsystems and back to said first variable delay elements, wherein each said time measuring sub-circuits comprises:
- (i) a storage capacitor coupled to said first current source so as to be charged by said charging current output and to said second current source via a voltage-controlled switch so as to be discharged by said discharging current output,
- (ii) a second variable delay element coupled to a corresponding one of said transmission lines and responsive to a voltage across said storage capacitor, said second variable delay element being effective for issuing a disconnect signal to said voltage-controlled switch a delay time after the initiating of current flow in said corresponding transmission line, said delay time being proportional to the voltage across said storage capacitor, said second current source being initially coupled to said storage capacitor and being disconnected from said storage capacitor in response to said disconnect signal,
- whereby said charging current output, said discharging current output, and said second variable delay element form a closed loop circuit for adjusting the charge on said storage capacitor until the amount of charge removed from the storage capacitor by the discharging current output is substantially similar to the amount of charge added to the storage capacitor by the charging current output, wherein the voltage across the capacitor is a measure of said current flow time for the corresponding transmission line;
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- a time calculating control component coupled to each time measuring sub-circuits for determining one-half said current flow time and subtracting said one-half current flow time from a predetermined maximum delay time, the resultant value being a variable delay control signal coupled to a corresponding one of said first variable delay elements, each of said first variable delay elements being effective for delaying said clock timing events by an amount determined by said variable delay control signal, whereby the total time delay for said clock timing events from said output points through the respective first variable delay elements and transmission lines to said plurality of digital subsystems is substantially equalized to said predetermined maximum delay time.