Low-jitter random clock generation circuit

A low-jitter random clock generation circuit, comprising:

• a clock division and pulse generation module, configured to:
• be connected to an input clock, perform frequency division processing on the input clock to obtain a plurality of frequency division clocks, and then detect some frequency division clocks one by one to obtain a plurality of frequency division pulses in a one-to-one correspondence;
• a pseudorandom number generation module, configured to:
• be connected to one frequency division clock, and generate a pseudorandom number based on the frequency division clock;
• a status control module, configured to:
• be connected to all the frequency division clocks and the pseudorandom number, and generate a plurality of status control signals based on the frequency division clocks and the pseudorandom number;
• and
• a random clock output module, configured to:
• be connected to the input clock, all the frequency division clocks, all the frequency division pulses, and all the status control signals, randomly sample the frequency division clocks by using the frequency division pulses under control of the status control signals, and synchronously output the randomly sampled frequency division clocks by using the input clock, to obtain random clocks.