Clock control circuit, memory, and clock control method

A clock control circuit, applied to a memory, comprising:

• a delay adjustment circuit, configured to receive a first phase clock signal, a second phase clock signal, a third phase clock signal, a fourth phase clock signal, and a determination result signal, adjust delays of the second phase clock signal, the third phase clock signal, and the fourth phase clock signal or adjust delays of the first phase clock signal, the second phase clock signal, and the fourth phase clock signal according to the determination result signal when the memory is in a duty cycle adjustment training mode, and output a first target clock signal, a second target clock signal, a third target clock signal, and a fourth target clock signal;
• and
• a determination circuit, electrically connected with the delay adjustment circuit, and configured to record a phase sequence of the first phase clock signal and the third phase clock signal at self-refresh exit timing of the memory, then compare the phase sequence of the first phase clock signal and the third phase clock signal at the self-refresh exit timing with a phase sequence of the first phase clock signal and the third phase clock signal at previous self-refresh exit timing, and output the determination result signal according to whether the two phase sequences are consistent or not.