H03K 5/1508
Using a plurality of delay lines
Official title: {using a plurality of delay lines}
H03K5/1508 (Using a plurality of delay lines) appears on 79 US grants and 50 published applications in this corpus.
Search patents in H03K- Granted patents
- 79
- Published applications
- 50
- Assignees
- 41
- Inventors
- 140
- Latest grant
- 26 Aug 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1985 | 1 | 0 |
| 1986 | 1 | 0 |
| 1987 | 2 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 1 | 0 |
| 1993 | 2 | 0 |
| 1994 | 4 | 0 |
| 1995 | 2 | 0 |
| 1996 | 2 | 0 |
| 1997 | 0 | 0 |
| 1998 | 4 | 0 |
| 1999 | 1 | 0 |
| 2000 | 0 | 0 |
| 2001 | 1 | 0 |
| 2002 | 0 | 0 |
| 2003 | 1 | 4 |
| 2004 | 2 | 3 |
| 2005 | 3 | 4 |
| 2006 | 1 | 1 |
| 2007 | 2 | 1 |
| 2008 | 4 | 2 |
| 2009 | 1 | 2 |
| 2010 | 3 | 4 |
| 2011 | 4 | 2 |
| 2012 | 3 | 1 |
| 2013 | 1 | 1 |
| 2014 | 2 | 1 |
| 2015 | 3 | 1 |
| 2016 | 1 | 1 |
| 2017 | 1 | 2 |
| 2018 | 5 | 6 |
| 2019 | 8 | 5 |
| 2020 | 3 | 0 |
| 2021 | 0 | 0 |
| 2022 | 0 | 1 |
| 2023 | 4 | 5 |
| 2024 | 2 | 2 |
| 2025 | 3 | 1 |
By publication year. Applications have been published since 2001.
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Most cited
By later US patents
- Skew-free clock signal distribution network in a microprocessor172US 5,307,381 AIntel Corporation · 1994
- Circuit for determining clock propagation delay in a transmission line126US 6,219,384 B12001
- Clock signal duty cycle correction circuit and method102US 5,757,218 AInternational Business Machines Corporation · 1998
- Method and apparatus for complete functional testing of a complex signal path of a semiconductor chip73US 5,198,758 ADigital Equipment Corporation · 1993
- Method and apparatus for clock skew reduction through absolute delay regulation62US 5,272,390 ADigital Equipment Corporation · 1993