Method and apparatus for clock skew reduction through absolute delay regulation
AssigneeDigital Equipment Corporation
InventorsRichard B. Watson, Jr., Hansel A. Collins, Russell Iknaian
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Abstract
An "absolute" delay regulator of a clock repeater chip performs a precise measurement of the propagation delay of a clock signal and adjusts that delay so as to maintain a fixed-phase relationship with an input clock signal. A replica loop accurately replicates the internal path and external loading, including input and output buffers, of the chip. The output of the replica loop drives a delay line whose tapped outputs provide an absolute delay measurement. Results of the measurement are decoded and used to select an appropriate tap to another delay line used to insert a desired amount of delay to an output clock signal.
Claims18
An absolute delay regulator circuit for reducing clock skew, in a synchronous computer system, during a delay regulation cycle, said computer having a plurality of modules, each of the modules having a clock repeater chip configured to receive, process and distribute system clock signals having a substantially constant phase relationship to various circuitry of that module, said absolute delay regulator circuit being located on said clock repeater chip and comprising:
- a control logic unit configured to generate timing signals used during the sequencing of operations of said delay regulation cycle;
- a replica loop circuit including a plurality of logic circuitry segments configured to substantially simulate intrinsic propagation delays of an internal clock path of said repeater chip;
- a measurement circuit coupled to said replica loop circuit for measuring said simulated intrinsic propagation delays during a measurement cycle, said measurement circuit including a tapped measurement delay line connected to a measurement latch and decoder circuit;
- a measurement reference generator for supplying a measurement reference signal to said replica loop circuit and said measurement circuit;
- a pair of delay adjusting units connected to receive the output of said measurement latch and decoder circuit, each of said delay adjusting units including a control register, a tap select multiplexer and a clock delay line, said control register control to said tap select multiplexer having inputs connected to respective taps of said clock delay line located in the path of said system clock signals that propagate through said internal clock path, said control registers responding to selected ones of said timing signals generated by said control logic unit such that one of said pair of delay adjusting units adds a controlled amount of delay to said system clock signals as the other of said pair determines said intrinsic propagation delay from a previous measurement cycle;
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- a clock delay multiplexer having a plurality of inputs coupled to an output of each of said tap select multiplexers for selecting the one of said plurality of clock delay multiplexer inputs providing said delayed system clock signals for distribution to said circuitry of the modules such that said constant phase relationship is maintained among said delayed system clock signals.
Dependencies are inferred from the claim text.