Pipeline clock driving circuit, computing chip, hashboard, and computing device

A pipeline clock driving circuit, configured to provide a pulse clock signal for a pipeline comprising a plurality of operation stages, the pipeline clock driving circuit comprising:

• a plurality of stages of clock driving circuits, wherein each stage of clock driving circuit is configured to provide the pulse clock signal to a corresponding operation stage of the plurality of operation stages of the pipeline;
• and
• a clock source, coupled to an input of a first-stage clock driving circuit and configured to provide a basic clock signal, wherein
• an input of each stage of clock driving circuit other than the first-stage clock driving circuit in the plurality of stages of clock driving circuits is coupled to an output of a previous-stage clock driving circuit, and
• wherein each stage of clock driving circuit comprises:
• a trigger, coupled to an input of a current-stage clock driving circuit;
• a delay module, comprising a first delay sub-module, wherein the first delay sub-module is coupled to an output of the trigger and delays a pulse signal output by the trigger, and feeds a delayed pulse signal back to the trigger as a feedback pulse signal;
• and
• a combinational logic module, coupled to outputs of the trigger and the first delay sub-module, the combinational logic module performing a combinational logic operation on the pulse signal output by the trigger and the feedback pulse signal output by the first delay sub-module to generate the pulse clock signal to be provided to a corresponding operation stage of the pipeline, and
• in each stage of clock driving circuit other than a last-stage clock driving circuit in the plurality of stages of clock driving circuits, the delay module further comprises a second delay sub-module, and the second delay sub-module is coupled to the output of the trigger and delays the pulse signal output by the trigger, and outputs the delayed pulse signal to a next-stage clock driving circuit as a clock driving signal.