Adjustable clock phase for peak-current reduction

A configurable circuit product, the configurable circuit product having a non-transitory machine-readable storage medium that stores circuit configuration instructions, the circuit configuration instructions being readable by a field programmable gate array device to initialize a circuit that comprises:

• a first logic block;
• and
• a routing block that routes a clock signal to the first logic block, the routing block including a selectable delay circuit with a plurality of delay paths and a multiplexer that selects one of the plurality of delay paths, wherein each of the plurality of delay paths delays the clock signal by a different amount.

A method for configuring a circuit device, comprising:

• placing and routing circuit design components, including a first logic block, a second logic block, wherein the first logic block and the second logic block each receive a clock signal;
• selecting a first phase delay path for the clock signal to the first logic block and a second phase delay path for the clock signal to the second logic block, the first phase delay path and the second phase delay path having different delay times, to cause the first logic block and the second logic block to trigger out of phase.