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US 2024/0085939 A1Published application
Clock generating circuit and clock distribution network and semiconductor apparatus including the clock generating circuit
AssigneeSK hynix Inc.
InventorsYeon Ho LEE, Yong Suk CHOI
Life of this patent
Estimating the term…
Abstract
A clock generating circuit includes a buffer circuit and a phase compensating circuit. The buffer circuit buffers an input clock signal to generate an output clock signal. The phase compensating circuit detects a noise in a power voltage and adjusts, according to the noise of the power voltage, a voltage level of the input clock signal to compensate for a phase change of the output clock signal due to the noise of the power voltage.
Claims23
A clock generating circuit comprising:
- a buffer circuit configured to buffer an input clock signal to generate an output clock signal;
- a voltage control circuit configured to detect a voltage level change of a power voltage and configured to generate a first control voltage and a second control voltage, the first control voltage and the second control voltage having varying voltage levels according to the detected voltage level change;
- and
- to a compensating circuit configured to adjust a phase of the input clock signal based on the output clock signal, the first control voltage, and the second control voltage.
1 more element
A clock generating circuit comprising:
- a first buffer circuit configured to buffer a first input clock signal to generate a first output clock signal;
- a second buffer circuit configured to buffer a second input clock signal to generate a second output clock signal, the second input clock signal being a complementary clock signal of the first input clock signal;
- a voltage control circuit configured to detect a voltage level change of a power voltage and configured to generate a first control voltage and a second control voltage, the first control voltage and the second control voltage having varying voltage levels according to the detected voltage level change;
- and
- a compensating circuit configured to change voltage levels of the first input clock signal and the second input clock signal based on the first output clock signal, the second output clock signal, the first control voltage, and the second control voltage.
2 more elements
A semiconductor apparatus including a clock distribution network,
- wherein the clock distribution network includes:
- a clock receiving circuit configured to receive an external clock signal and a complementary external clock signal to generate a first input clock signal and a second input clock signal;
- a first buffer circuit configured to buffer the first input clock signal to generate a first output clock signal;
- a second buffer circuit configured to buffer the second input clock signal to generate a second output clock signal;
- a phase compensating circuit configured to detect a voltage level change of a power voltage, configured to delay phases of the first input signal and the second input clock signal as the voltage level of the power voltage is raised and configured to advance the phases of the first input signal and the second input clock signal as the voltage level of the power voltage is lowered;
- and
- a dividing circuit configured to divide the first output clock signal and the second output clock signal to generate a plurality of internal clock signals.
4 more elements
Dependencies are inferred from the claim text.