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US 12,189,416 B2Granted
Clock generating circuit and clock distribution network and semiconductor apparatus including the clock generating circuit
AssigneeSK hynix Inc.
InventorsYeon Ho Lee, Yong Suk Choi
Life of this patent
Estimating the term…
Abstract
A clock generating circuit includes a buffer circuit and a phase compensating circuit. The buffer circuit buffers an input clock signal to generate an output clock signal. The phase compensating circuit detects a noise in a power voltage and adjusts, according to the noise of the power voltage, a voltage level of the input clock signal to compensate for a phase change of the output clock signal due to the noise of the power voltage.
Claims18
A clock generating circuit comprising:
- a buffer circuit configured to non-invert an input clock signal to generate an output clock signal;
- a voltage control circuit configured to detect a voltage level change of a power voltage and configured to generate a first control voltage and a second control voltage, the first control voltage and the second control voltage having varying voltage levels according to the detected voltage level change;
- and
- a compensating circuit configured to invert the output clock signal according to the first and second control voltages to generate a feedback signal using a single inversion stage, and configured to provide the feedback signal to the input clock signal,
- wherein the feedback signal is a single inversion of the output clock signal.
2 more elements
A clock generating circuit comprising:
- a first buffer circuit configured to non-invert a first input clock signal to generate a first output clock signal;
- a second buffer circuit configured to non-invert a second input clock signal to generate a second output clock signal, the second input clock signal being a complementary clock signal of the first input clock signal;
- a voltage control circuit configured to detect a voltage level change of a power voltage and configured to generate a first control voltage and a second control voltage, the first control voltage and the second control voltage having varying voltage levels according to the detected voltage level change;
- a first compensating circuit configured to invert the first output clock signal according to the first and second control voltages to generate a first feedback signal using a single inversion stage, and configured to provide the first feedback signal to the first input clock signal;
- and
- a second compensating circuit configured to invert the second output clock signal according to the first and second control voltages to generate a second feedback signal, and configured to provide the second feedback signal to the second input clock signal,
- wherein the first feedback signal is a single inversion of the first output clock signal.
4 more elements
A semiconductor apparatus including a clock distribution network,
- wherein the clock distribution network includes:
- a clock receiving circuit configured to receive an external clock signal and a complementary external clock signal to generate a first input clock signal and a second input clock signal;
- a first buffer circuit configured to non-invert the first input clock signal to generate a first output clock signal;
- a second buffer circuit configured to non-invert the second input clock signal to generate a second output clock signal;
- a voltage control circuit configured to detect a voltage level change of a power voltage and configured to generate a first control voltage and a second control voltage, the first control voltage and the second control voltage having varying voltage levels according to the detected voltage level change;
- a first compensating circuit configured to invert the first output clock signal according to the first and second control voltages to generate a first feedback signal using a single inversion stage, and configured to provide the first feedback signal to the first input clock signal;
- a second compensating circuit configured to invert the second output clock signal according to the first and second control voltages to generate a second feedback signal, and configured to provide the second feedback signal to the second input clock signal;
- and
- a dividing circuit configured to divide the first output clock signal and the second output clock signal to generate a plurality of internal clock signals,
- wherein the first feedback signal is a single inversion of the first output clock signal.
7 more elements
Dependencies are inferred from the claim text.