US 5,198,758 AGranted

Method and apparatus for complete functional testing of a complex signal path of a semiconductor chip

AssigneeDigital Equipment Corporation

InventorsRussell Iknaian, Richard B. Watson, Jr.

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Abstract

A test register coupled to an absolute delay regulator circuit of a clock repeater chip enables complete functional testing of a clock delay path of the regulator. The test register is connected to a measurement latch of the clock path in a "logical OR" configuration with respect to a measurement delay line and is enabled during a test mode by control logic of the repeater chip. Operationally, a sequence of logic "0" bits are forced in the measurement delay line during test mode. A state machine clears the measurement latch, and then loads a test pattern into the test register. As each bit of the register is set, a corresponding bit in the measurement latch is also set to simulate a measurement cycle; the results of the "measurement" are stored in the measurement latch. Once the test pattern is loaded, the repeater chip is placed into a measurement test mode. Execution of a measurement test cycle then propagates the test pattern throughout the clock delay path of the regulator. An output clock signal is sampled and if determined present, indicates that the clock path column under test is functional. Each column of the clock path is then tested separately in sequence.

Claims11

Dependent claims

Method for testing logic devices of a complex signal path of a semiconductor chip, said logic devices including at least a measurement latch circuit, said method comprising the steps of:

placing said chip in a test mode in response to first control signals and forcing a sequence of unasserted bits into a measurement delay line circuit having signal outputs connected to said measurement latch circuit, and further placing said chip in a plurality of sub-test modes in response to second control signals to enable complete functional testing of said logic devices of said complex signal path;
shifting a selected pattern of asserted bits into a test register, located on said chip, in response to a clocking signal, said test register being connected to said measurement latch circuit, said selected pattern of asserted bits comprising a test pattern;
loading said test pattern from said test register into said measurement latch circuit and thereafter into said logic devices of said complex signal path when said chip is placed in a measurement test sub-mode of said test mode, said test pattern overriding the signal outputs of said measurement delay line;
generating timing signals with a control logic unit to activate said logic devices of said signal path during said measurement sub-mode;
and
sampling an output clock signal of said chip to determine whether said clock signal is present at the output line of said chip, whereby the presence of said output clock signal indicates that said logic devices of said complex signal path exercised by said test pattern are functional.

3 more elements

Apparatus for testing logic circuits in a complex signal path in a semiconductor chip, said logic circuits including a measurement latch and decoder circuit connected to a plurality of delay adjusting units configured to produce a delay-regulated clock signal at the output of said chip, the sequencing of operations of said logic circuits being initiated by a signal path control logic unit in accordance with a measurement regulation cycle, said apparatus comprising:

a test register located on said chip, said test register having a serial input connected to a source of a signal in a predetermined logical state and having a plurality of outputs connected to corresponding ones of a plurality of inputs of latch devices of said measurement latch and decoder circuit, said latch devices further having a plurality of outputs connected to corresponding inputs of a decoder circuit of said measurement latch and decoder circuit;
and
a mode control logic unit for placing said semiconductor chip in a test mode of operation in response to first control signals, said mode control logic unit further generating first and second timing signals in response to a plurality of second control signals that place said semiconductor chip in a plurality of sub-test modes of operation, said sub-test modes of operation including:
a reset mode for placing said signal path control logic unit in a known state of said measurement regulation cycle in response to said first timing signal;
a shift mode for loading a pattern of said predetermined logical signal states into said test register in response to said second timing signal;
and
a measurement test mode for loading said pattern of predetermined logical signal states from said test register into said logic circuits of said signal path in accordance with said measurement regulation cycle,
wherein said pattern of predetermined logical signal states propagates through said logic circuits and said delay-regulated clock signal at the output of said chip is sampled to determine successful testing of said logic circuits.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/764,314Filed 23 Sep 1991
Granted: 30 Mar 1993
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H03K 17/005
Switching arrangements with several input- or output terminals: with several inputs only
G01R 31/3016
Marginal testing, e.g. by varying supply voltage: delay or race condition test, e.g. race hazard test
G01R 31/31725
Testing of digital circuits: timing aspects, e.g. clock distribution, skew, propagation delay
G06F 1/08
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency