Apparatus and method for monitoring duty cycle of memory clock signal
AssigneeElectronics and Telecommunications Research Institute
InventorsMin-Hyung Cho, Yi-Gyeong Kim, Su-Jin Park, Young-Deuk Jeon
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Abstract
Disclosed herein are an apparatus and method for monitoring the duty cycle of a memory clock signal. The apparatus for monitoring a duty cycle of a memory clock signal includes a clock frequency converter configured to generate a second monitoring target clock signal by decreasing a frequency of a first monitoring target clock signal while maintaining a duty cycle of the first monitoring target clock signal, and a pulse counter configured to measure a pulse width of the second monitoring target clock signal using a reference clock signal.
Claims6
An apparatus for monitoring a duty cycle of a memory clock signal, comprising:
- a clock frequency converter configured to generate a second monitoring target clock signal by decreasing a frequency of a first monitoring target clock signal while maintaining a duty cycle of the first monitoring target clock signal;
- and
- a pulse counter configured to measure a pulse width of the second monitoring target clock signal using the first monitoring target clock signal,
- wherein the clock frequency converter comprises a plurality of half clock generators connected in cascade, each of the half clock generators being configured to output a clock signal by decreasing a frequency of an input clock signal to half while maintaining a duty cycle of the input clock signal,
- wherein each of the half clock generators comprises:
- a clock divider configured to decrease the frequency of the input clock signal to half;
- a pulse width doubler configured to double a pulse width of the input clock signal;
- and
- an AND gate configured to perform a logical AND operation on an output signal of the clock divider and an output signal of the pulse width doubler.
A method for monitoring a duty cycle of a memory clock signal, comprising:
- generating a second monitoring target clock signal by decreasing a frequency of a first monitoring target clock signal while maintaining a duty cycle of the first monitoring target clock signal;
- and
- measuring a pulse width of the second monitoring target clock signal using the first monitoring target clock signal,
- wherein generating the second monitoring target clock signal comprises:
- performing a plurality of times an operation of decreasing a frequency of a clock signal to half while maintaining a duty cycle of the clock signal,
- wherein decreasing the frequency of the clock signal to half while maintaining the duty cycle of the clock signal comprises:
- generating a first output signal by decreasing the frequency of the clock signal to half;
- generating a second output signal by doubling a pulse width of the clock signal;
- and
- performing a logical AND operation on the first output signal and the second output signal.
A device for converting a frequency of a duty cycle monitoring target clock signal, wherein:
- the device is configured to generate a second monitoring target clock signal by decreasing a frequency of a first monitoring target clock signal while maintaining a duty cycle of the first monitoring target clock signal, and
- the device comprises a plurality of half clock generators connected in cascade, each of the half clock generators being configured to output a clock signal by decreasing a frequency of an input clock signal to half while maintaining a duty cycle of the input clock signal,
- wherein each of the half clock generators comprises:
- a clock divider configured to decrease the frequency of the input clock signal to half;
- a pulse width doubler configured to double a pulse width of the input clock signal;
- and
- an AND gate configured to perform a logical AND operation on an output signal of the clock divider and an output signal of the pulse width doubler.
Dependencies are inferred from the claim text.