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US 2026/0291480 A1Published application
Symmetric high-speed quadrature divider with feedforward path and sub-rate phase detection
AssigneeAlphawave IP Inc.
InventorJoshua LIANG
Life of this patent
Estimating the term…
Abstract
A clock generation circuit includes latches and summing circuits. A first latch may be clocked by a first phase version of a clock signal and a second latch may be clocked by a second phase version of the clock signal. A first summing circuit may have a first input that is coupled to an output of the first latch, a second input that is coupled to an input of the first latch, and an output that is coupled to an input of the second latch.
Claims20
A clock generation circuit, comprising:
- a first latch that is configured to be clocked by a first phase version of a clock signal;
- a second latch that is configured to be clocked by a second phase version of the clock signal;
- and
- a first summing circuit having a first input that is coupled to an output of the first latch, a second input that is coupled to an input of the first latch, and an output that is coupled to an input of the second latch.
1 more element
An apparatus comprising:
- means for sequentially clocking a plurality of latches;
- and
- means for capturing by a first latch in the plurality of latches, a sum of an input and an output of a second latch in the plurality of latches.
A method for generating clock signals, comprising:
- clocking a first latch using a first phase version of a clock signal;
- clocking a second latch using a second phase version of the clock signal;
- and
- capturing a sum of an output of the first latch and an input of the first latch at the second latch responsive to a transition in the second phase version of the clock signal.
1 more element
Dependencies are inferred from the claim text.