Clock transmission circuit, imaging element, and method for manufacturing clock transmission circuit

A clock transmission circuit including a clock tree provided on a single substrate, the clock transmission circuit comprising:

• a plurality of circuit regions that have circuit patterns and are arranged in one direction,
• wherein each of the circuit patterns of the plurality of circuit regions has
• at least two circuit elements that are switchable between a high impedance state and a pass state, and
• wirings that are connected to the circuit patterns of circuit regions adjacent to concerned circuit region, among the plurality of circuit regions,
• wherein states of the at least two circuit elements of the plurality of circuit regions are controlled to be predetermined states determined for each circuit region, so that at least a part of the clock tree crossing the plurality of circuit regions is configured,
• wherein the circuit pattern includes a plurality of stages of circuit portions configured to take on a plurality of stages of branches of the clock tree, respectively,
• wherein at least one circuit portion among the plurality of stages of circuit portions includes
• third circuit element, fourth circuit element, and fifth circuit element that are included in the at least two circuit elements,
• wherein an output end of the third circuit element, an input end of the fourth circuit element, and an input end of the fifth circuit element are connected to a second node,
• wherein an input end of the third circuit element and an output end of the fourth circuit element are connected to a third node, and
• wherein the wirings include
• a third wiring portion for connecting the second node, to the third node of a circuit region adjacent to one side of the concerned circuit region, among the plurality of circuit regions, and
• a fourth wiring portion for connecting the third node, to the second node of a circuit region adjacent to another side of the concerned circuit region, among the plurality of circuit regions.

A method for manufacturing a clock transmission circuit including a clock tree provided on a single substrate, the method comprising:

• a step of performing stitch exposure to form a plurality of circuit regions that have circuit patterns and are arranged in one direction,
• wherein each of the circuit patterns of the plurality of circuit regions has
• at least two circuit elements that are switchable between a high impedance state and a pass state, and
• wirings that are connected to the circuit patterns of circuit regions adjacent to concerned circuit region, among the plurality of circuit regions,
• wherein states of the at least two circuit elements of the plurality of circuit regions are controlled to be predetermined states determined for each circuit region, so that at least a part of the clock tree crossing the plurality of circuit regions is configured,
• wherein the circuit pattern includes a plurality of stages of circuit portions configured to take on a plurality of stages of branches of the clock tree, respectively,
• wherein one circuit portion among the plurality of stages of circuit portions includes
• first circuit element and second circuit element that are included in the at least two circuit elements and have output ends connected to each other, and
• wherein the wirings include
• a first wiring portion for connecting an input end of the first circuit element, to an input end of the second circuit element of a circuit region adjacent to one side of the concerned circuit region, among the plurality of circuit regions, and
• a second wiring portion for connecting an input end of the second circuit element, to an input end of the first circuit element of a circuit region adjacent to another side of the concerned circuit region, among the plurality of circuit regions.

A method for manufacturing a clock transmission circuit including a clock tree provided on a single substrate, the method comprising:

• a step of performing stitch exposure to form a plurality of circuit regions that have circuit patterns and are arranged in one direction,
• wherein each of the circuit patterns of the plurality of circuit regions has
• at least two circuit elements that are switchable between a high impedance state and a pass state, and
• wirings that are connected to the circuit patterns of circuit regions adjacent to concerned circuit region, among the plurality of circuit regions,
• wherein states of the at least two circuit elements of the plurality of circuit regions are controlled to be predetermined states determined for each circuit region, so that at least a part of the clock tree crossing the plurality of circuit regions is configured,
• wherein the circuit pattern includes a plurality of stages of circuit portions configured to take on a plurality of stages of branches of the clock tree, respectively,
• wherein at least one circuit portion among the plurality of stages of circuit portions includes
• third circuit element, fourth circuit element, and fifth circuit element that are included in the at least two circuit elements,
• wherein an output end of the third circuit element, an input end of the fourth circuit element, and an input end of the fifth circuit element are connected to a second node,
• wherein an input end of the third circuit element and an output end of the fourth circuit element are connected to a third node, and
• wherein the wirings include
• a third wiring portion for connecting the second node, to the third node of a circuit region adjacent to one side of the concerned circuit region, among the plurality of circuit regions, and
• a fourth wiring portion for connecting the third node, to the second node of a circuit region adjacent to another side of the concerned circuit region, among the plurality of circuit regions.