G11C 8/18
Address timing or clocking circuits
Official title: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
G11C8/18 (Address timing or clocking circuits) appears on 2,400 US grants and 1,764 published applications in this corpus.
Search patents in G11C- Granted patents
- 2,400
- Published applications
- 1,764
- Assignees
- 359
- Inventors
- 2,830
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 1 | 0 |
| 1980 | 1 | 0 |
| 1981 | 1 | 0 |
| 1982 | 5 | 0 |
| 1983 | 3 | 0 |
| 1984 | 6 | 0 |
| 1985 | 5 | 0 |
| 1986 | 20 | 0 |
| 1987 | 24 | 0 |
| 1988 | 24 | 0 |
| 1989 | 21 | 0 |
| 1990 | 28 | 0 |
| 1991 | 25 | 0 |
| 1992 | 24 | 0 |
| 1993 | 29 | 0 |
| 1994 | 47 | 0 |
| 1995 | 37 | 0 |
| 1996 | 44 | 0 |
| 1997 | 57 | 0 |
| 1998 | 53 | 0 |
| 1999 | 63 | 0 |
| 2000 | 69 | 0 |
| 2001 | 68 | 23 |
| 2002 | 63 | 59 |
| 2003 | 58 | 45 |
| 2004 | 47 | 39 |
| 2005 | 35 | 42 |
| 2006 | 37 | 37 |
| 2007 | 47 | 60 |
| 2008 | 38 | 52 |
| 2009 | 34 | 82 |
| 2010 | 62 | 102 |
| 2011 | 76 | 57 |
| 2012 | 76 | 75 |
| 2013 | 84 | 99 |
| 2014 | 95 | 90 |
| 2015 | 103 | 79 |
| 2016 | 97 | 71 |
| 2017 | 99 | 77 |
| 2018 | 67 | 78 |
| 2019 | 97 | 102 |
| 2020 | 114 | 72 |
| 2021 | 83 | 89 |
| 2022 | 77 | 94 |
| 2023 | 83 | 87 |
| 2024 | 78 | 64 |
| 2025 | 64 | 56 |
| 2026 | 29 | 33 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
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- Control signal training22 Sep 2026US 12,744,067 B2Cadence Design Systems, Inc.
- Stack memory devices communicating via packets15 Sep 2026US 12,738,304 B2SK hynix Inc.
- Memory device for outputting data and operating method thereof18 Aug 2026US 12,711,054 B2SK hynix Inc.
- Method, device, and circuit for high-speed memories4 Aug 2026US 12,700,442 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Apparatus, memory controller, memory device, memory system, and method for clock switching and low power consumption17 Sep 2026US 2026/0279420 A1Samsung Electronics Co., Ltd.
- Semiconductor apparatus having a clock distribution network3 Sep 2026US 2026/0260678 A1SK hynix Inc.
- System application of dram component with cache mode13 Aug 2026US 2026/0237423 A1Rambus Inc.
- Memory system, control method thereof, and program30 Jul 2026US 2026/0221202 A1Kioxia Corporation
- Dram interface mode with improved channel integrity and efficiency at high signaling rates23 Jul 2026US 2026/0212901 A1Rambus Inc.
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- System for transporting information objects between a user station and multiple remote sources based upon user modifiable object manifest stored in the user station372US 6,125,388 A2000
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