Method, device, and circuit for high-speed memories
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJaspal Singh Shah, Atul Katoch
Life of this patent
Estimating the term…
Abstract
A memory device includes a plurality of memory cells arranged in an array, a first clock generator connected to the plurality of memory cells and configured to generate a local clock signal to be provided to the plurality of memory cells, a second clock generator connected to an input/output interface connected to the plurality of memory cells, the second clock generator configured to generate a global clock signal to be provided to the input/output interface, and one or more logic gates connected to at least one of the first clock generator or the second clock generator, wherein the one or more logic gates allow the local clock signal and the global clock signal to be output independently.
Claims20
A memory device, comprising:
- a plurality of memory cells arranged in an array;
- a first clock generator connected to the plurality of memory cells and configured to generate a local clock signal to be provided to the plurality of memory cells;
- a second clock generator connected to an input/output interface connected to the plurality of memory cells, the second clock generator configured to generate a global clock signal to be provided to the input/output interface;
- and
- one or more logic gates connected to at least one of the first clock generator or the second clock generator such that the first clock generator and the second clock generator are to output the local clock signal and the global clock signal independently according to at least a design for testability (DFT) enable signal.
A circuit, comprising:
- a first clock generator configured to generate a local clock signal according to an input clock signal, a chip enable bar (CEB) signal, and a design for testability (DFT) enable signal;
- a second clock generator configured to generate a global clock signal according to the input clock signal, the CEB signal, and the DFT enable signal;
- and
- one or more logic gates configured to cause the first clock generator and the second clock generator to independently generate the local clock signal and the global clock signal according to the input clock signal, the CEB signal, and the DFT enable signal,
- wherein at least one of the DFT enable signal of a logic high state or the CEB signal of a logic low state is configured to trigger an activation of the global clock signal including a signal enabling a test mode operation of the circuit.
A method, comprising:
- receiving an input clock signal, a chip enable bar (CEB) signal, and a design for testability (DFT) enable signal;
- generating a first enable signal to cause a first clock generator to activate a local clock signal, based on a logic high state of a first set of signals among the input clock signal, the CEB signal, and the DFT enable signal;
- and
- generating a second enable signal to cause a second clock generator to activate a global clock signal, based on a logic high state of a second set of signals among the input clock signal, the CEB signal, and the DFT enable signal,
- wherein generation of the first enable signal and the second enable signal are independent.
Dependencies are inferred from the claim text.