Stack memory devices communicating via packets
AssigneeSK hynix Inc.
InventorChoung Ki Song
Life of this patent
Estimating the term…
Abstract
A stack memory device includes a command control circuit configured to latch a command and an address in synchronization with a clock signal to generate a latch command and a latch address, decode the latch command and the latch address to generate a decoding command that is transmitted through a first interface, and encode the decoding command to generate a row control signal and a column control signal that are transmitted through a second interface, and a core control circuit configured to, based on the row control signal and the column control signal, control internal operations performed on a core chip.
Claims24
A stack memory device comprising:
- a command control circuit configured to:
- latch a command and an address in synchronization with a clock signal to generate a latch command and a latch address,
- decode the latch command and the latch address to generate a decoding command that is transmitted through a first interface and to generate data to a parallelization circuit, and
- encode the decoding command to generate a row control signal and a column control signal that are transmitted through a second interface;
- and
- a core control circuit configured to, based on the row control signal and the column control signal, control internal operations performed on a core chip,
- wherein the parallelization circuit is configured to receive the data serially to generate parallelized internal data.
A stack memory device comprising:
- a command decoder configured to decode a latch command and a latch address to generate a decoding command that is transmitted through a first interface and to generate data to a parallelization circuit;
- a command encoder configured to encode the decoding command to generate a row control signal and a column control signal that are transmitted through a second interface;
- and
- a core control circuit configured to, based on the row control signal and the column control signal, control internal operations performed on a core chip,
- wherein the parallelization circuit is configured to receive the data serially to generate parallelized internal data.
A stack memory device comprising:
- a command decoder configured to:
- decode a latch command and a latch address to generate a decoding command that is transmitted through a first interface and data to a parallelization circuit,
- generate a data input control signal to perform a write operation on the core chip, and
- generate a data output control signal to perform a read operation on the core chip;
- a command encoder configured to encode the decoding command to generate a row control signal and a column control signal that are transmitted through a second interface;
- and
- a core control circuit configured to, based on the data input control signal, the data output control signal, the row control signal, and the column control signal, control internal operations performed on the core chip,
- wherein the parallelization circuit is configured to receive the data serially to generate parallelized internal data.
A stack memory device comprising:
- a base chip;
- and
- a core chip stacked on the base chip and electrically connected to the base chip,
- wherein the base chip comprises:
- a command control circuit configured to:
- latch a command and an address in synchronization with a clock signal to generate a latch command and a latch address,
- decode the latch command and the latch address to generate a decoding command that is transmitted through a first interface and to generate data to a parallelization circuit, and
- encode the decoding command to generate a row control signal and a column control signal that are transmitted through a second interface;
- and
- a core control circuit configured to, based on the row control signal and the column control signal, control internal operations performed on the core chip,
- wherein the parallelization circuit is configured to receive the data serially to generate parallelized internal data.
Dependencies are inferred from the claim text.